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| author | Marc Jones <marcj303@gmail.com> | 2017-04-20 16:48:42 -0600 |
|---|---|---|
| committer | Marc Jones <marc@marcjonesconsulting.com> | 2017-04-26 04:14:12 +0200 |
| commit | 6fcaaef6140aca68603f57d1c684c3381d472ac4 (patch) | |
| tree | 3c642feacf9b7782d1232ffdd30843b491d46ec0 | |
| parent | c1f32336e62c846073bdb0d92b54a84ac7320c3c (diff) | |
| download | coreboot-6fcaaef6140aca68603f57d1c684c3381d472ac4.tar.gz coreboot-6fcaaef6140aca68603f57d1c684c3381d472ac4.tar.bz2 coreboot-6fcaaef6140aca68603f57d1c684c3381d472ac4.zip | |
amd/pi/hudson: Add TPM decode to SPI function
Add a function to send the TPM decode to the SPI interface.
Enables use of SPI TPMs on Hudson mainboards.
Change-Id: I0e85ed92163e38eca6a55456708ab322d6a90d4c
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19402
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/southbridge/amd/pi/hudson/early_setup.c | 9 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/hudson.h | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/lpc.c | 7 |
3 files changed, 16 insertions, 4 deletions
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 5f3f0ee858d5..b5e753d22224 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -327,4 +327,13 @@ void hudson_read_mode(u32 mode) & ~SPI_READ_MODE_MASK) | mode); } +void hudson_tpm_decode_spi(void) +{ + device_t dev = PCI_DEV(0, 0x14, 3); /* LPC device */ + + u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); + pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase + | ROUTE_TPM_2_SPI); +} + #endif diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 6b6343bc10bd..baed2c30ad48 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -69,6 +69,7 @@ #define REV_HUDSON_A12 0x12 #define SPIROM_BASE_ADDRESS_REGISTER 0xA0 +#define ROUTE_TPM_2_SPI BIT(3) #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 @@ -188,8 +189,7 @@ void hudson_disable_4dw_burst(void); void hudson_set_readspeed(u16 norm, u16 fast); void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); - - +void hudson_tpm_decode_spi(void); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); #if IS_ENABLED(CONFIG_HUDSON_UART) diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index d73979cd9756..60a1b88bae03 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -126,10 +126,13 @@ static void hudson_lpc_read_resources(device_t dev) static void hudson_lpc_set_resources(struct device *dev) { struct resource *res; + u32 spi_enable_bits; - /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ + /* Special case. The SpiRomEnable and other enables should STAY set. */ res = find_resource(dev, 2); - pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE); + spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); + spi_enable_bits &= 0xF; + pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | spi_enable_bits); pci_dev_set_resources(dev); } |