intel/kblrvp: Enable audio in RVP7 and RVP3

Enable audio:
* Add verb table for ALC286 & ALC298
* Enable virtual channel 1 for DmiVc1 & HdaVc1.

TEST= Build for kblrvp3 as well as kblrvp7. Boot to OS & verified
working of audio on both the boards.

Change-Id: Id27e3cf585b93ed4131d7bf3d3b53d3f5404b18e
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/18875
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

6 files changed, 490 insertions, 0 deletions

diff --git a/src/mainboard/intel/kblrvp/Makefile.inc b/src/mainboard/intel/kblrvp/Makefile.inc
index 7ddfb9fa91c8..6da41ae02f9a 100644
--- a/src/mainboard/intel/kblrvp/Makefile.inc
+++ b/src/mainboard/intel/kblrvp/Makefile.inc
@@ -31,6 +31,8 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 ramstage-y += mainboard.c
 ramstage-y += ramstage.c
 
+ramstage-y += hda_verb.c
+
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
 subdirs-y += variants/$(VARIANT_DIR)
diff --git a/src/mainboard/intel/kblrvp/hda_verb.c b/src/mainboard/intel/kblrvp/hda_verb.c
new file mode 100644
index 000000000000..8a87968f7fc8
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/hda_verb.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation
+ * (Written by Naresh G Solanki <naresh.solanki@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootstate.h>
+#include <chip.h>
+#include <console/console.h>
+#include <device/azalia_device.h>
+#include <soc/intel/common/hda_verb.h>
+#include <soc/pci_devs.h>
+
+#include "variant/hda_verb.h"
+
+static void codecs_init(u8 *base, u32 codec_mask)
+{
+	int i;
+
+	/* Can support up to 4 codecs */
+	for (i = 3; i >= 0; i--) {
+		if (codec_mask & (1 << i))
+			hda_codec_init(base, i, cim_verb_data_size,
+					cim_verb_data);
+	}
+
+	if (pc_beep_verbs_size)
+		hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);
+}
+
+static void mb_hda_codec_init(void *unused)
+{
+	static struct soc_intel_skylake_config *config;
+	u8 *base;
+	struct resource *res;
+	u32 codec_mask;
+	struct device *dev;
+
+	dev = SA_DEV_ROOT;
+	/* Check if HDA is enabled, else return */
+	if (dev == NULL || dev->chip_info == NULL)
+		return;
+
+	config = dev->chip_info;
+
+	/*
+	 * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port,
+	 * 3:I2S Ports. In HDA mode where codec need to be programmed with
+	 * verb table
+	 */
+	if (config->IoBufferOwnership == 3)
+		return;
+
+	/* Find base address */
+	dev = dev_find_slot(0, PCH_DEVFN_HDA);
+	if (dev == NULL)
+		return;
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	if (!res)
+		return;
+
+	base = res2mmio(res, 0, 0);
+	printk(BIOS_DEBUG, "HDA: base = %p\n", base);
+
+	codec_mask = hda_codec_detect(base);
+
+	if (codec_mask) {
+		printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask);
+		codecs_init(base, codec_mask);
+	}
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL);
diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c
index 3a48396d2227..d733341f4abd 100644
--- a/src/mainboard/intel/kblrvp/ramstage.c
+++ b/src/mainboard/intel/kblrvp/ramstage.c
@@ -25,6 +25,9 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 	 * dependencies during hardware initialization. */
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 	params->CdClock = 3;
+
+	/* Enable Virtual Channel 1 */
+	params->PchHdaVcType = 0x1;
 }
 
 static void ioexpander_init(void *unused)
diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c
index 2e0292daf7c6..a3b1ba1f91a4 100644
--- a/src/mainboard/intel/kblrvp/romstage.c
+++ b/src/mainboard/intel/kblrvp/romstage.c
@@ -58,4 +58,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 		mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0];
 	}
 	mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+
+	mupd->FspmTestConfig.DmiVc1 = 1;
 }
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h
new file mode 100644
index 000000000000..9d6e8b00ec9e
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h
@@ -0,0 +1,200 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation
+ * (Written by Naresh G Solanki <naresh.solanki@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+
+	0x8086280B,
+	0x00000000,
+	0x00000005,
+
+	/*
+	 * Display Audio Verb Table
+	 * Enable the third converter and pin first (NID 08h)
+	 */
+	0x00878101,
+	0x00878101,
+	0x00878101,
+	0x00878101,
+
+	AZALIA_PIN_CFG(0, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(0, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(0, 0x07, 0x18560030),
+
+	/* Disable the third converter and third pin (NID 08h) */
+	0x00878100,
+	0x00878100,
+	0x00878100,
+	0x00878100,
+
+	/* ALC 286 */
+	0x10EC0286,
+	0x00000000,
+	0x00000023,
+
+	AZALIA_SUBVENDOR(0, 0x10EC108E),
+	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
+	AZALIA_PIN_CFG(0, 0x12, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x9017011F),
+	AZALIA_PIN_CFG(0, 0x17, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x03A11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x1A, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x1D, 0x4066A22D),
+	AZALIA_PIN_CFG(0, 0x1E, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x21, 0x03211020),
+
+	/* Widget node 0x20 */
+	0x02050071,
+	0x02040014,
+	0x02050010,
+	0x02040C22,
+	/* Widget node 0x20 - 1 */
+	0x0205004F,
+	0x02045029,
+	0x0205004F,
+	0x02045029,
+	/* Widget node 0x20 - 2 */
+	0x0205002B,
+	0x02040DD0,
+	0x0205002D,
+	0x02047020,
+	/* Widget node 0x20 - 3 */
+	0x0205000E,
+	0x02046C80,
+	0x01771F90,
+	0x01771F90,
+	/* TI AMP settings */
+	0x02050022,
+	0x0204004C,
+	0x02050023,
+	0x02040000,
+
+	0x02050025,
+	0x02040000,
+	0x02050026,
+	0x0204B010,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x02050022,
+	0x0204004C,
+	0x02050023,
+	0x02040002,
+
+	0x02050025,
+	0x02040011,
+	0x02050026,
+	0x0204B010,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x02050022,
+	0x0204004C,
+	0x02050023,
+	0x0204000D,
+
+	0x02050025,
+	0x02040010,
+	0x02050026,
+	0x0204B010,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x02050022,
+	0x0204004C,
+	0x02050023,
+	0x02040025,
+
+	0x02050025,
+	0x02040008,
+	0x02050026,
+	0x0204B010,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x02050022,
+	0x0204004C,
+	0x02050023,
+	0x02040002,
+
+	0x02050025,
+	0x02040000,
+	0x02050026,
+	0x0204B010,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x02050022,
+	0x0204004C,
+	0x02050023,
+	0x02040003,
+
+	0x02050025,
+	0x02040000,
+	0x02050026,
+	0x0204B010
+};
+
+const u32 pc_beep_verbs[] = {
+};
+AZALIA_ARRAY_SIZES;
+#endif
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h
new file mode 100644
index 000000000000..d0f68c83668c
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h
@@ -0,0 +1,200 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation
+ * (Written by Naresh G Solanki <naresh.solanki@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+
+	0x8086280B,
+	0x00000000,
+	0x00000005,
+
+	/*
+	 * Display Audio Verb Table
+	 * Enable the third converter and Pin first (NID 08h)
+	 */
+	0x00878101,
+	0x00878101,
+	0x00878101,
+	0x00878101,
+
+	AZALIA_PIN_CFG(0, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(0, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(0, 0x07, 0x18560030),
+
+	/* Disable the third converter and third Pin (NID 08h) */
+	0x00878100,
+	0x00878100,
+	0x00878100,
+	0x00878100,
+
+	/* ALC 286 */
+	0x10EC0286,
+	0x00000000,
+	0x00000023,
+
+	AZALIA_SUBVENDOR(0, 0x10EC1092),
+	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
+	AZALIA_PIN_CFG(0, 0x12, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x9017011F),
+	AZALIA_PIN_CFG(0, 0x17, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x03A11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x1A, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x1D, 0x4066A22D),
+	AZALIA_PIN_CFG(0, 0x1E, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x21, 0x03211020),
+
+	/* Widget node 0x20 */
+	0x02050071,
+	0x02040014,
+	0x02050010,
+	0x02040C22,
+	/* Widget node 0x20 - 1 */
+	0x0205004F,
+	0x02045029,
+	0x0205004F,
+	0x02045029,
+	/* Widget node 0x20 - 2 */
+	0x0205002B,
+	0x02040DD0,
+	0x0205002D,
+	0x02047020,
+	/* Widget node 0x20 - 3 */
+	0x0205000E,
+	0x02046C80,
+	0x01771F90,
+	0x01771F90,
+	/* TI AMP settings */
+	0x02050022,
+	0x0204004C,
+	0x02050023,
+	0x02040000,
+
+	0x02050025,
+	0x02040000,
+	0x02050026,
+	0x0204B010,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x02050022,
+	0x0204004C,
+	0x02050023,
+	0x02040002,
+
+	0x02050025,
+	0x02040011,
+	0x02050026,
+	0x0204B010,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x02050022,
+	0x0204004C,
+	0x02050023,
+	0x0204000D,
+
+	0x02050025,
+	0x02040010,
+	0x02050026,
+	0x0204B010,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x02050022,
+	0x0204004C,
+	0x02050023,
+	0x02040025,
+
+	0x02050025,
+	0x02040008,
+	0x02050026,
+	0x0204B010,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x02050022,
+	0x0204004C,
+	0x02050023,
+	0x02040002,
+
+	0x02050025,
+	0x02040000,
+	0x02050026,
+	0x0204B010,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+	0x000F0000,
+
+	0x02050022,
+	0x0204004C,
+	0x02050023,
+	0x02040003,
+
+	0x02050025,
+	0x02040000,
+	0x02050026,
+	0x0204B010
+};
+
+const u32 pc_beep_verbs[] = {
+};
+AZALIA_ARRAY_SIZES;
+#endif