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| author | Shelley Chen <shchen@chromium.org> | 2017-04-24 13:11:43 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-04-27 10:15:20 +0200 |
| commit | e8365aa283d6f18f124e89f6648d94d481de8cff (patch) | |
| tree | c6ddf7ad35be61b49125a50e924f1ebfbd07c4d9 | |
| parent | 771e8c114f8616ce67d78cb5f1df13aa44e90752 (diff) | |
| download | coreboot-e8365aa283d6f18f124e89f6648d94d481de8cff.tar.gz coreboot-e8365aa283d6f18f124e89f6648d94d481de8cff.tar.bz2 coreboot-e8365aa283d6f18f124e89f6648d94d481de8cff.zip | |
google/fizz: Enable SATA on port 1
BUG=b:37486021
BRANCH=None
TEST=compile coreboot and make sure sda and sdb show
up in /sys/class/block.
Change-Id: I11344a4a5fc7e5b5d907d25439f92744a5fb70da
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19450
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index a20203299bab..e18b76701e00 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -28,6 +28,7 @@ chip soc/intel/skylake register "SataSalpSupport" = "1" register "SataMode" = "1" register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" |