diff options
| author | Philipp Deppenwiese <zaolin@das-labor.org> | 2014-10-17 16:10:32 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-10-17 17:19:42 +0200 |
| commit | 93643e362d541b6ab32147e5886ca661a9eec1ac (patch) | |
| tree | 3cecd48a15019b3e5858518d901ffcb5b2ba34eb | |
| parent | 7f7fb6f9baea8df19190f637e1395658a6be0c4a (diff) | |
| download | coreboot-93643e362d541b6ab32147e5886ca661a9eec1ac.tar.gz coreboot-93643e362d541b6ab32147e5886ca661a9eec1ac.tar.bz2 coreboot-93643e362d541b6ab32147e5886ca661a9eec1ac.zip | |
Fix ICH spi implementation which reads data from different chips.
This patch adjusts the read timeout in order to support flash chips
which needs more than 60ms to complete a spi command.
This problem can be reproduced on a Thinkpad T520 with M25PX64 spi chip ( suspend to ram bug ).
Change-Id: I22b2e59f1855ead6162a292b83b9b854b55c0235
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: http://review.coreboot.org/7105
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
| -rw-r--r-- | src/southbridge/intel/common/spi.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 8e7192b49f34..2ea9a2414218 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -517,7 +517,7 @@ static int spi_setup_offset(spi_transaction *trans) } /* - * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set + * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set * below is True) or 0. In case the wait was for the bit(s) to set - write * those bits back, which would cause resetting them. * @@ -525,7 +525,7 @@ static int spi_setup_offset(spi_transaction *trans) */ static int ich_status_poll(u16 bitmask, int wait_til_set) { - int timeout = 6000; /* This will result in 60 ms */ + int timeout = 600000; /* This will result in 6 seconds */ u16 status = 0; while (timeout--) { @@ -538,7 +538,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) udelay(10); } - printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", + printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, bitmask %x\n", status, bitmask); return -1; } |