This patch should serve as a porting help for other northbridges for the new resource allocator.

file-by-file changes:

dts:
	There are no bus devices, remove it.  Add the northbridge devices.
	Fix susbsytem_vendor and subsystem_device.

southbridge/intel/i82371eb/ide:
	Make the ide enabled by default.

northbridge/intel/i440bxemulation/i440bx.c:
	1. Split ops into domain and northbridge
		A. Domain should have bus ops, scan_bus, etc.
		B. Northbridge should have ops for its own registers.
			In this case it only needs read and set resources.

functions:
	i440bx_read_resources - set up the IO and VGA resources.  VGA is fixed.
	i440bx_ram_resources - this should be called after resource assignment.
	i440bx_set_resources - call pci_set_resources then i440bx_ram_resources.
	i440bx_domain_read_resources - Set up system-wide resources, and
		reserve space for the local APIC.  I put the IOAPIC here too,
		but it belongs somewhere in the southbridge.
	i440bx_domain_set_resources - Mark the domain-specific resources as
		stored (In a real device you'd probably need to set some
		registers here.)  Call phase4_set_resources for children.

southbridge/intel/i82371eb/i82371eb.c:
	1. Add ISA read and set resources to reserve legacy IO space.
		- Note that since it's subtractively decoded, it doesn't need
		to be stored anywhere.  It needs to be marked stored so
		pci_set_resource doesn't try to store it.
	
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1092 f3766cd6-281f-0410-b1cd-43a5c92072e9

8 files changed, 214 insertions, 37 deletions

diff --git a/mainboard/emulation/qemu-x86/dts b/mainboard/emulation/qemu-x86/dts
index 056de21c217d..b65b41bf0b32 100644
--- a/mainboard/emulation/qemu-x86/dts
+++ b/mainboard/emulation/qemu-x86/dts
@@ -21,21 +21,25 @@
 /{
 	mainboard_vendor = "Emulation";
 	mainboard_name = "QEMU x86";
-	mainboard_pci_subsystem_vendor = "0x15ad";
-	mainboard_pci_subsystem_device = "0x1976";
+	subsystem_vendor = "0x15ad";
+	subsystem_device = "0x1976";
 	device_operations = "qemuvga_pci_ops_dev";
 	cpus {};
 	domain@0 {
 		/config/("northbridge/intel/i440bxemulation/domain");
-		bus@0 {
-			pci@0,0 {
-			};
-			pci@1,1 {
-				/config/("southbridge/intel/i82371eb/ide");
-				subsystem_vendor = "0x15ad";
-				subsystem_device = "0x1976";
-				on_mainboard;
-			};
+		pci@0,0 {
+			/config/("northbridge/intel/i440bxemulation/northbridge");
 		};
+		pci@1,0 {
+			/config/("southbridge/intel/i82371eb/isa");
+		};
+		pci@1,1 {
+			/config/("southbridge/intel/i82371eb/ide");
+		};
+		pci@1,3 {
+			/config/("southbridge/intel/i82371eb/acpi");
+		};
+		/* PCI 2.0 and 3.0 are plugged in. */
+		/* 2.0 is the Cirrus VGA card.  3.0 is a nic. */
 	};
 };
diff --git a/northbridge/intel/i440bxemulation/i440bx.c b/northbridge/intel/i440bxemulation/i440bx.c
index 513fc72e586b..34eb4fa5807f 100644
--- a/northbridge/intel/i440bxemulation/i440bx.c
+++ b/northbridge/intel/i440bxemulation/i440bx.c
@@ -56,30 +56,103 @@ static int inb_cmos(int port)
 	return inb(0x71);
 }
 
-static void pci_domain_set_resources(struct device *dev)
+static void no_op(struct device *dev)
+{
+}
+
+static void i440bx_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	/* Hole for VGA (0xA0000-0xAFFFF) graphics and text mode
+	 * graphics (0xB8000-0xBFFFF) */
+	res = new_resource(dev, 1);
+	res->base = 0xA0000UL;
+	res->size = 0x20000UL;
+	res->limit = 0xBFFFUL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+}
+
+static void i440bx_ram_resources(struct device *dev)
 {
-	struct device *mc_dev;
 	u32 tolmk;		/* Top of low mem, Kbytes. */
 	int idx;
-	/* read large mem memory descriptor
-	   for <16 MB read the more detailed small mem descriptor
-	   all values in kbytes */
+
+	/* Read the large mem memory descriptor.  If that value is <16 MB, read
+	 * the more detailed small mem descriptor.  All values are in kbytes.
+	 */
 	tolmk = ((inb_cmos(0x35)<<8) |inb_cmos(0x34)) * 64;
 	if (tolmk <= 16 * 1024) {
 		tolmk = (inb_cmos(0x31)<<8) |inb_cmos(0x30);
 	}
-	printk(BIOS_WARNING, "Ignoring chipset specified RAM size. Using dts "
-		"settings of %d kB instead.\n", tolmk);
-	mc_dev = dev->link[0].children;
-	if (mc_dev) {
-		idx = 10;
-		/* 0 .. 640 kB */
-		ram_resource(dev, idx++, 0, 640);
-		/* Hole for VGA (0xA0000-0xAFFFF) graphics and text mode
-		 * graphics (0xB8000-0xBFFFF) */
-		/* 768 kB .. Systop (in KB) */
-		ram_resource(dev, idx++, 768, tolmk - 768);
-	}
+
+	printk(BIOS_WARNING, "Using CMOS settings of %d kB RAM.\n", tolmk);
+	idx = 10;
+
+	/* 0 .. 640 kB */
+	ram_resource(dev, idx++, 0, 640);
+
+	/* 768 kB .. Systop (in KB) */
+	ram_resource(dev, idx++, 768, tolmk - 768);
+}
+
+static void i440bx_set_resources(struct device *dev)
+{
+	/* If there were any NB-specific resources that were not part of the
+	 * domain, they would get set here.
+	 */
+
+	pci_set_resources(dev);
+
+	/* Add RAM resources. They are not part of resource allocation. */
+	i440bx_ram_resources(dev);
+
+	/* If RAM values need to be set, do it here. */
+}
+
+static void i440bx_domain_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	pci_domain_read_resources(dev);
+
+	/* Reserve space for the IOAPIC.  This should be in the Southbridge,
+	 * but I couldn't tell which device to put it in. */
+	res = new_resource(dev, 2);
+	res->base = 0xfec00000UL;
+	res->size = 0x100000UL;
+	res->limit = 0xffffffffUL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+		     IORESOURCE_ASSIGNED;
+
+	/* Reserve space for the LAPIC.  There's one in every processor, but
+	 * the space only needs to be reserved once, so we do it here. */
+	res = new_resource(dev, 3);
+	res->base = 0xfee00000UL;
+	res->size = 0x10000UL;
+	res->limit = 0xffffffffUL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+		     IORESOURCE_ASSIGNED;
+}
+
+static void i440bx_domain_set_resources(struct device *dev)
+{
+	struct resource *res;
+
+	/* If the domain needs these resources set in BARs, do it here. */
+
+	/* Domain I/O resource. */
+	res = probe_resource(dev,0);
+	if (res)
+		res->flags |= IORESOURCE_STORED;
+
+	/* Domain Memory resource. */
+	res = probe_resource(dev,1);
+	if (res)
+		res->flags |= IORESOURCE_STORED;
+
 	phase4_set_resources(&dev->link[0]);
 }
 
@@ -90,10 +163,24 @@ struct device_operations i440bx_domain = {
 		{.pci_domain = {.vendor = 0x8086,.device = 0x7190}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = pci_domain_scan_bus,
-	.phase4_read_resources	 = pci_domain_read_resources,
-	.phase4_set_resources	 = pci_domain_set_resources,
+	.phase4_read_resources	 = i440bx_domain_read_resources,
+	.phase4_set_resources	 = i440bx_domain_set_resources,
 	.phase5_enable_resources = enable_childrens_resources,
-	.phase6_init		 = 0,
+	.phase6_init		 = no_op,
+	.ops_pci_bus		 = &pci_cf8_conf1,
+
+};
+
+/* Here are the operations for the northbridge. */
+struct device_operations i440bx_northbridge = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = 0x8086,.device = 0x1237}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = NULL,
+	.phase4_read_resources	 = i440bx_read_resources,
+	.phase4_set_resources	 = i440bx_set_resources,
+	.phase5_enable_resources = no_op,
+	.phase6_init		 = no_op,
 	.ops_pci_bus		 = &pci_cf8_conf1,
 
 };
diff --git a/northbridge/intel/i440bxemulation/i440bx.h b/northbridge/intel/i440bxemulation/i440bx.h
index ca9cd48f38f1..9ea97e573957 100644
--- a/northbridge/intel/i440bxemulation/i440bx.h
+++ b/northbridge/intel/i440bxemulation/i440bx.h
@@ -92,6 +92,4 @@
 #define PAM5    0x5e
 #define PAM6    0x5f
 
-unsigned int i440bx_scan_root_bus(struct device *root, unsigned int max);
-
 #endif /* NORTHBRIDGE_INTEL_I440BXEMULATION_I440BX_H */
diff --git a/northbridge/intel/i440bxemulation/northbridge b/northbridge/intel/i440bxemulation/northbridge
new file mode 100644
index 000000000000..e179d47b4e2f
--- /dev/null
+++ b/northbridge/intel/i440bxemulation/northbridge
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "i440bx_northbridge";
+};
diff --git a/southbridge/intel/i82371eb/acpi b/southbridge/intel/i82371eb/acpi
new file mode 100644
index 000000000000..cb30df05a30d
--- /dev/null
+++ b/southbridge/intel/i82371eb/acpi
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "i82371eb_acpi";
+};
diff --git a/southbridge/intel/i82371eb/i82371eb.c b/southbridge/intel/i82371eb/i82371eb.c
index 62e1949d173e..41228e18614b 100644
--- a/southbridge/intel/i82371eb/i82371eb.c
+++ b/southbridge/intel/i82371eb/i82371eb.c
@@ -83,6 +83,25 @@ static void i82371eb_acpi_init(struct device *dev)
 	pci_write_config8(dev, 0x80, 1);
 }
 
+static void i82371eb_isa_read_resources(struct device *dev)
+{
+	struct resource *res;
+	res = new_resource(dev, 0);
+	res->base = 0x0UL;
+	res->size = 0x1000UL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
+		     IORESOURCE_STORED;
+}
+
+static void i82371eb_isa_set_resources(struct device *dev)
+{
+	/* If the isa resource needed to be set somehow in hardware, we would do
+	 * it here.  We would call probe_resource(dev,0), then set it in
+	 * hardware before calling pci_set_resources.
+	 */
+	pci_set_resources(dev);
+}
+
 /*NOTE: We need our own read and set resources for this part! It has 
  * BARS that are not in the normal place (such as SMBUS)
  */
@@ -92,8 +111,8 @@ struct device_operations i82371eb_isa = {
 		{.pci = {.vendor = 0x8086,.device = 0x7000}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = 0,
-	.phase4_read_resources	 = pci_dev_read_resources,
-	.phase4_set_resources	 = pci_set_resources,
+	.phase4_read_resources	 = i82371eb_isa_read_resources,
+	.phase4_set_resources	 = i82371eb_isa_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
 	.phase6_init		 = i82371eb_isa_init,
 	.ops_pci		 = &pci_dev_ops_pci,
diff --git a/southbridge/intel/i82371eb/ide b/southbridge/intel/i82371eb/ide
index 41253e19d38d..ba6caca1dd1a 100644
--- a/southbridge/intel/i82371eb/ide
+++ b/southbridge/intel/i82371eb/ide
@@ -19,7 +19,7 @@
  */
 
 {
-	ide0_enable = "0";
-	ide1_enable = "0";
+	ide0_enable = "1";
+	ide1_enable = "1";
 	device_operations = "i82371eb_ide";
 };
diff --git a/southbridge/intel/i82371eb/isa b/southbridge/intel/i82371eb/isa
new file mode 100644
index 000000000000..a7e20894da50
--- /dev/null
+++ b/southbridge/intel/i82371eb/isa
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "i82371eb_isa";
+};