diff options
| author | Ronald G. Minnich <rminnich@gmail.com> | 2009-02-18 21:17:22 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2009-02-18 21:17:22 +0000 |
| commit | 2fe48ba7d566e7f0a2b2c62837ce659ebad6365e (patch) | |
| tree | 034628330857372ff547e15f241280b933cf331d | |
| parent | b6c89edb049dfad3ac642fb2bc449d593df9b491 (diff) | |
| download | coreboot-2fe48ba7d566e7f0a2b2c62837ce659ebad6365e.tar.gz coreboot-2fe48ba7d566e7f0a2b2c62837ce659ebad6365e.tar.bz2 coreboot-2fe48ba7d566e7f0a2b2c62837ce659ebad6365e.zip | |
Add this file from v2. Not build tested, just want to get it in.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1134 f3766cd6-281f-0410-b1cd-43a5c92072e9
| -rw-r--r-- | arch/x86/secondary.S | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/arch/x86/secondary.S b/arch/x86/secondary.S new file mode 100644 index 000000000000..14ec3cc654ec --- /dev/null +++ b/arch/x86/secondary.S @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Linux Networx + * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx) + * Copyright (C) 2004 Ollie Lo + * Copyright (C) 2005 YingHai Lu + * Copyright (C) Copyright (C) 2005-2007 Stefan Reinauer <stepan@openbios.org> + * Copyright (C) 2009 Ronald G. Minnich <rminnich@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + .text + .globl _secondary_start, _secondary_start_end + .balign 4096 +_secondary_start: + .code16 + cli + xorl %eax, %eax + movl %eax, %cr3 /* Invalidate TLB*/ + + /* On hyper threaded cpus, invalidating the cache here is + * very very bad. Don't. + */ + + /* setup the data segment */ + movw %cs, %ax + movw %ax, %ds + + data32 lgdt gdtaddr - _secondary_start + + movl %cr0, %eax + andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x60000001, %eax /* CD, NW, PE = 1 */ + movl %eax, %cr0 + + ljmpl $0x10, $1f +1: + .code32 + movw $0x18, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + + /* Load the Interrupt descriptor table */ + lidt idtarg + + /* Set the stack pointer, and flag that we are done */ + xorl %eax, %eax + movl secondary_stack, %esp + movl %eax, secondary_stack + + call secondary_cpu_init +1: hlt + jmp 1b + + gdtaddr: + .word gdt_limit /* the table limit */ + .long gdt /* we know the offset */ + +_secondary_start_end: +.code32 |