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| author | Ronald G. Minnich <rminnich@gmail.com> | 2009-02-24 03:38:37 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2009-02-24 03:38:37 +0000 |
| commit | 52bdacea134c881228f9617cfb6ba19b6d2a9e9f (patch) | |
| tree | 0a5ed2672b01cae09919a6e122ec22790c96caa3 | |
| parent | bee5429ba647a0f29d98530f57ef1771939ceb30 (diff) | |
| download | coreboot-52bdacea134c881228f9617cfb6ba19b6d2a9e9f.tar.gz coreboot-52bdacea134c881228f9617cfb6ba19b6d2a9e9f.tar.bz2 coreboot-52bdacea134c881228f9617cfb6ba19b6d2a9e9f.zip | |
Again, this probably won't work but I want to make the code visible so
people can suggest what's wrong.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1139 f3766cd6-281f-0410-b1cd-43a5c92072e9
| -rw-r--r-- | arch/x86/intel/core2/init_cpus.c | 4 | ||||
| -rw-r--r-- | arch/x86/secondary.S | 7 |
2 files changed, 6 insertions, 5 deletions
diff --git a/arch/x86/intel/core2/init_cpus.c b/arch/x86/intel/core2/init_cpus.c index b5e0548cde60..89ddd4282f55 100644 --- a/arch/x86/intel/core2/init_cpus.c +++ b/arch/x86/intel/core2/init_cpus.c @@ -287,7 +287,7 @@ static int lapic_start_cpu(unsigned long apicid, u32 *secondary_base) /* Boot on the stack */ /* Kick the second */ - printk(BIOS_SPEW, "Send start_eip %#lx(%#lx)\n", start_eip, start_eip>>12); + printk(BIOS_SPEW, "Send start_eip %#lx(%#lx) sb[-1] %p\n", start_eip, start_eip>>12, (void *) secondary_base[-1]); lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP | (start_eip >> 12)); @@ -321,7 +321,7 @@ static int lapic_start_cpu(unsigned long apicid, u32 *secondary_base) if (send_status || accept_status) break; } - printk(BIOS_SPEW, "After Startup.\n"); + printk(BIOS_SPEW, "After Startup.sb[-1] %p\n", (void *) secondary_base[-1]); if (send_status) printk(BIOS_WARNING, "APIC never delivered???\n"); if (accept_status) diff --git a/arch/x86/secondary.S b/arch/x86/secondary.S index 8c9ea898fbe1..7d795cfd3976 100644 --- a/arch/x86/secondary.S +++ b/arch/x86/secondary.S @@ -24,12 +24,13 @@ .text .globl _secondary_start, _secondary_start_end _secondary_start: +1: .code16 .balign 4096 cli + movl $1b, %ebx xorl %eax, %eax movl %eax, %cr3 /* Invalidate TLB*/ - /* On hyper threaded cpus, invalidating the cache here is * very very bad. Don't. */ @@ -60,8 +61,8 @@ secondary32: lidt idtarg /* Set the stack pointer */ - movl $_secondary_start-4,%eax - movl 0x0(%eax),%esp + movl -4(%ebx),%esp + movl $0, -4(%ebx) call secondary_cpu_init 1: hlt |