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| author | Marc Jones <marcj303@gmail.com> | 2009-01-20 00:03:11 +0000 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2009-01-20 00:03:11 +0000 |
| commit | b8562cfb7bc7caccb3f1fee2ba5a4a26ea41d43a (patch) | |
| tree | c75ccfb1c04b73e9d8d4e23facbc36fe442abd6b | |
| parent | 67d036327d60649df19966b3949e83b2ac94a678 (diff) | |
| download | coreboot-b8562cfb7bc7caccb3f1fee2ba5a4a26ea41d43a.tar.gz coreboot-b8562cfb7bc7caccb3f1fee2ba5a4a26ea41d43a.tar.bz2 coreboot-b8562cfb7bc7caccb3f1fee2ba5a4a26ea41d43a.zip | |
One missed function rename in the stage2 pci resources allocation. phase4_assign_resources is now phase4_set_resources. (trivial)
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1117 f3766cd6-281f-0410-b1cd-43a5c92072e9
| -rw-r--r-- | northbridge/via/cn700/pci_domain.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/northbridge/via/cn700/pci_domain.c b/northbridge/via/cn700/pci_domain.c index 9f16e48fc2f2..f7759b25e838 100644 --- a/northbridge/via/cn700/pci_domain.c +++ b/northbridge/via/cn700/pci_domain.c @@ -114,7 +114,7 @@ static void cn700_pci_domain_set_resources(struct device *dev) /* TODO: shadow ram needs to be controlled via dts */ ram_resource(dev, idx++, 1024, (tolmk - 1024 - (CONFIG_CN700_VIDEO_MB * 1024))); - phase4_assign_resources(&dev->link[0]); + phase4_set_resources(&dev->link[0]); } /** Operations for when the northbridge is running a PCI domain. */ |