Start of Artec Group ThinCan DBE63 support.

* Copying of files from other mainboards as a starting point:
amd/db800/Makefile
artecgroup/dbe62/cmos.layout
artecgroup/dbe62/dts
amd/db800/initram.c
artecgroup/dbe61/irq_tables.h
artecgroup/dbe62/stage1

* Kconfig integration. Behind CONFIG_EXPERIMENTAL for now, as the board is not in the market yet.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1119 f3766cd6-281f-0410-b1cd-43a5c92072e9

7 files changed, 449 insertions, 0 deletions

diff --git a/mainboard/artecgroup/Kconfig b/mainboard/artecgroup/Kconfig
index 567e1bd249d4..fe7acea80d13 100644
--- a/mainboard/artecgroup/Kconfig
+++ b/mainboard/artecgroup/Kconfig
@@ -43,6 +43,17 @@ config BOARD_ARTECGROUP_DBE62
 	help
 	  Artec Group DBE62 ThinCan.
 
+config BOARD_ARTECGROUP_DBE63
+	bool "DBE63"
+	select ARCH_X86
+	select CPU_AMD_GEODELX
+	select NORTHBRIDGE_AMD_GEODELX
+	select SOUTHBRIDGE_AMD_CS5536
+	select PIRQ_TABLE
+	depends EXPERIMENTAL
+	help
+	  Artec Group DBE63 ThinCan.
+
 endchoice
 
 config MAINBOARD_DIR
@@ -54,3 +65,8 @@ config MAINBOARD_DIR
 	string
 	default artecgroup/dbe62
 	depends BOARD_ARTECGROUP_DBE62
+
+config MAINBOARD_DIR
+	string
+	default artecgroup/dbe63
+	depends BOARD_ARTECGROUP_DBE63
diff --git a/mainboard/artecgroup/dbe63/Makefile b/mainboard/artecgroup/dbe63/Makefile
new file mode 100644
index 000000000000..a8bd1db04f5c
--- /dev/null
+++ b/mainboard/artecgroup/dbe63/Makefile
@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006-2007 coresystems GmbH
+## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
+
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+		$(src)/northbridge/amd/geodelx/raminit.c \
+		$(src)/southbridge/amd/cs5536/smbus_initram.c \
+		$(src)/arch/x86/geodelx/geodelx.c
+
+STAGE2_MAINBOARD_SRC = 
+
+$(obj)/coreboot.vpd:
+	$(Q)printf "  BUILD   DUMMY VPD\n"
+	$(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
+
diff --git a/mainboard/artecgroup/dbe63/cmos.layout b/mainboard/artecgroup/dbe63/cmos.layout
new file mode 100644
index 000000000000..5ba4c032c188
--- /dev/null
+++ b/mainboard/artecgroup/dbe63/cmos.layout
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+1008         16      h       0        check_sum
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
diff --git a/mainboard/artecgroup/dbe63/dts b/mainboard/artecgroup/dbe63/dts
new file mode 100644
index 000000000000..8089e791f344
--- /dev/null
+++ b/mainboard/artecgroup/dbe63/dts
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/{
+	mainboard_vendor = "Artec";
+	mainboard_name = "DBE62";
+	cpus { };
+	apic@0 {
+		/config/("northbridge/amd/geodelx/apic");
+	};
+	domain@0 {
+		/config/("northbridge/amd/geodelx/domain");
+		pci@1,0 {
+			/config/("northbridge/amd/geodelx/pci");
+			/* Video RAM has to be in 2MB chunks. */
+			geode_video_mb = "16";
+		};
+		pci@1,1 {
+			/* This is the graphics device, but since the memory
+			 * controller needs to know geode_video_mb, the
+			 * phase2_init is done there.  The rest are default ops.
+			 */
+		};
+		pci@1,2 { /* AES */
+		};
+		pci@f,0 {
+			/config/("southbridge/amd/cs5536/dts");
+			/* Interrupt enables for LPC bus.
+			 *  Each bit is an IRQ 0-15. */
+			lpc_serirq_enable = "0x00001002";
+			/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
+			lpc_serirq_polarity = "0x0000EFFD";
+			/* 0:continuous 1:quiet */
+			lpc_serirq_mode = "1";
+			/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. 
+			 * See virtual PIC spec. */
+			enable_gpio_int_route = "0x0D0C0700";
+			/* 0:IDE; 1:FLASH on CS0, 2:FLASH on CS1, 3:FLASH on CS2, 4:FLASH on CS3. */
+			enable_ide_nand_flash = "2";
+			/* we use com2 since that is on the dongle */
+			com2_enable = "1";
+			/* Set com2 address to be COM1 */
+			com2_address = "0x3f8";
+			/* Set com2 IRQ to be what is usually COM1 */
+			com2_irq = "4";
+			/* USB Port Power Handling setting. */
+			pph = "0xf5";
+		};
+		pci@f,1 {
+			/config/("southbridge/amd/cs5536/nand");
+		};
+	};
+};
diff --git a/mainboard/artecgroup/dbe63/initram.c b/mainboard/artecgroup/dbe63/initram.c
new file mode 100644
index 000000000000..34f3308f1836
--- /dev/null
+++ b/mainboard/artecgroup/dbe63/initram.c
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define _MAINOBJECT
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <amd_geodelx.h>
+#include <northbridge/amd/geodelx/raminit.h>
+
+/* #include <device/smbus.h>
+ * TODO: figure out how smbus functions should be done. See smbus_ops.c
+ */
+extern int smbus_read_byte(u16 device, u8 address);
+
+#define MANUALCONF 0		/* Do automatic strapped PLL config */
+#define PLLMSRHI 0x00001490	/* manual settings for the PLL */
+#define PLLMSRLO 0x02000030
+#define DIMM0 ((u8) 0xA0)
+#define DIMM1 ((u8) 0xA2)
+
+/**
+ * Read a byte from the SPD. 
+ *
+ * For this board, that is really just saying 'read a byte from SMBus'.
+ * So we use smbus_read_byte(). Nota Bene: leave this here as a function 
+ * rather than a #define in an obscure location. This function is called 
+ * only a few dozen times, and it's not performance critical. 
+ *
+ * @param device The device.
+ * @param address The address.
+ * @return The data from the SMBus packet area or an error of 0xff (i.e. -1).
+ */
+u8 spd_read_byte(u16 device, u8 address)
+{
+	u8 spdbyte;
+
+	printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device);
+
+	spdbyte = smbus_read_byte(device, address);
+
+	printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbyte);
+
+	return spdbyte;
+}
+
+/**
+  * Placeholder in case we ever need it. Since this file is a
+  * template for other motherboards, we want this here and we want the
+  * call in the right place.
+  */
+
+static void mb_gpio_init(void)
+{
+	/* Early mainboard specific GPIO setup */
+}
+
+/**
+  * main for initram for the AMD DB800 development platform.
+  * It might seem that you could somehow do these functions in, e.g., the cpu
+  * code, but the order of operations and what those operations are is VERY
+  * strongly mainboard dependent. It's best to leave it in the mainboard code.
+  */
+int main(void)
+{
+	printk(BIOS_DEBUG, "Hi there from initram (stage1) main!\n");
+	post_code(POST_START_OF_MAIN);
+
+	system_preinit();
+	printk(BIOS_DEBUG, "done preinit\n");
+
+	mb_gpio_init();
+	printk(BIOS_DEBUG, "done gpio init\n");
+
+	pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
+	printk(BIOS_DEBUG, "done pll reset\n");
+
+	cpu_reg_init(0, DIMM0, DIMM1, DRAM_UNTERMINATED);
+	printk(BIOS_DEBUG, "done cpu reg init\n");
+
+	sdram_set_registers();
+	printk(BIOS_DEBUG, "done sdram set registers\n");
+
+	sdram_set_spd_registers(DIMM0, DIMM1);
+	printk(BIOS_DEBUG, "done sdram set spd registers\n");
+
+	sdram_enable(DIMM0, DIMM1);
+	printk(BIOS_DEBUG, "done sdram enable\n");
+
+	/* Check low memory */
+	/*ram_check(0x00000000, 640*1024); */
+
+	printk(BIOS_DEBUG, "stage1 returns\n");
+	return 0;
+}
diff --git a/mainboard/artecgroup/dbe63/irq_tables.h b/mainboard/artecgroup/dbe63/irq_tables.h
new file mode 100644
index 000000000000..4649ef00324e
--- /dev/null
+++ b/mainboard/artecgroup/dbe63/irq_tables.h
@@ -0,0 +1,66 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright (C) 2007 Advanced Micro Devices, Inc.
+* Copyright (C) 2008 Artec Design LLC.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+*/
+
+#include <pirq_routing.h>
+
+/* Number of slots and devices in the PIR table */
+#define IRQ_SLOT_COUNT 3
+
+/* Platform IRQs */
+#define PIRQA 11
+#define PIRQB 10
+#define PIRQC 9
+#define PIRQD 5
+
+/* Map */
+#define M_PIRQA (1 << PIRQA)	/* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB)	/* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC)	/* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD)	/* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1		/* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2		/* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3		/* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4		/* Means Slot INTx# Connects To Chipset INTD# */
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,  /* u32 signature */
+	PIRQ_VERSION,    /* u16 version   */
+	32 + 16 * IRQ_SLOT_COUNT,	/* Max. number of devices on the bus */
+	0x00,			/* Where the interrupt router lies (bus) */
+	(0x0F << 3) | 0x0,	/* Where the interrupt router lies (dev) */
+	0x00,			/* IRQs devoted exclusively to PCI usage */
+	0x1022,			/* Vendor */
+	0x208f,			/* Device */
+	0,		/* Crap (miniport) */
+	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
+	0xf8,         /* Checksum */
+	{
+		/* If you change the number of entries, change IRQ_SLOT_COUNT above! */
+		/* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
+		// Geode GX3 Host Bridge and VGA Graphics
+		{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+		// Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio.
+		{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
+		// Realtek RTL8100/8139 Network Controller
+		{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+	}
+};
diff --git a/mainboard/artecgroup/dbe63/stage1.c b/mainboard/artecgroup/dbe63/stage1.c
new file mode 100644
index 000000000000..46864be41a0e
--- /dev/null
+++ b/mainboard/artecgroup/dbe63/stage1.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <amd_geodelx.h>
+#include <southbridge/amd/cs5536/cs5536.h>
+#include <northbridge/amd/geodelx/raminit.h>
+#include <arch/x86/msr.h>
+
+static const struct msrinit dbe62_msr[] = {
+	{.msrnum = 0x10000020, {.lo = 0x00fff80, .hi = 0x20000000}},
+	{.msrnum = 0x10000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
+	{.msrnum = 0x40000020, {.lo = 0x00fff80, .hi = 0x20000000}},
+	{.msrnum = 0x40000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
+};
+
+static void dbe62_msr_init(void)
+{
+	int i;
+	for (i = 0; i < ARRAY_SIZE(dbe62_msr); i++)
+		wrmsr(dbe62_msr[i].msrnum, dbe62_msr[i].msr);
+}
+
+void hardware_stage1(void)
+{
+	post_code(POST_START_OF_MAIN);
+
+	dbe62_msr_init();
+
+	cs5536_stage1();
+
+	/*
+	 * NOTE: Must do this AFTER the early_setup! It is counting on some
+	 * early MSR setup for the CS5536.
+	 */
+	cs5536_setup_onchipuart(2);
+
+	/* Set up 4MB mode for Artec LPC Dongle (this should be a no-op when not booting from the dongle) */
+	outb(0xf4,0x88);
+}
+
+void mainboard_pre_payload(void)
+{
+	geode_pre_payload();
+	banner(BIOS_DEBUG, "mainboard_pre_payload: done");
+}