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authorSean Rhodes <sean@starlabs.systems>2024-02-19 21:04:35 +0000
committerFelix Held <felix-coreboot@felixheld.de>2024-06-07 18:32:33 +0000
commit38170736e900a9110841447328e90348a99e19b2 (patch)
treef98b3680ed6396df1d80af0f100509c5667d9261
parentdf2c85f52b008f8a4f8e0c3a18706bb2217b5f6f (diff)
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mb/starlabs/labtop/cml: Increase TCC Offset
These values were configured based on a default value of 110, but for CML, it's actually 100. Adjust it accordingly. Change-Id: Ibffeeab67a7277625db9bdedca36d759ff0e72f6 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81414 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/starlabs/starbook/variants/cml/devtree.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
index 6985c67d163a..95a5d44ea3c7 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
@@ -22,17 +22,17 @@ void devtree_update(void)
disable_turbo();
soc_conf->tdp_pl1_override = 15;
soc_conf->tdp_pl2_override = 15;
- cfg->tcc_offset = 30;
+ cfg->tcc_offset = 20;
break;
case PP_BALANCED:
soc_conf->tdp_pl1_override = 17;
soc_conf->tdp_pl2_override = 20;
- cfg->tcc_offset = 25;
+ cfg->tcc_offset = 15;
break;
case PP_PERFORMANCE:
soc_conf->tdp_pl1_override = 20;
soc_conf->tdp_pl2_override = 25;
- cfg->tcc_offset = 20;
+ cfg->tcc_offset = 10;
break;
}