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| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-08-27 11:14:23 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-30 14:48:43 +0000 |
| commit | d145c95208b5129701a6a4125767fa0118083cf5 (patch) | |
| tree | ea29e51371e8128b69b30ea89f91c1c0f71d87d4 | |
| parent | 0e788c985c678f3f9ca84c192cd0fd04df30d70d (diff) | |
| download | coreboot-d145c95208b5129701a6a4125767fa0118083cf5.tar.gz coreboot-d145c95208b5129701a6a4125767fa0118083cf5.tar.bz2 coreboot-d145c95208b5129701a6a4125767fa0118083cf5.zip | |
soc/intel/cannonlake: Fix comment errors for SMBUS
On CannonLake PCH, SMBUS stays at Bus 0 Device 31 and Function 4,
previous comment in southbridge.asl mention it as Function 3 that was a
mistake.
BUG=N/A
TEST=N/A
Change-Id: I29786457379809b6fcb592e1136ff612539e24dc
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/southbridge.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 4a62485324c1..e4f29b6a37e1 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -37,7 +37,7 @@ /* Serial IO */ #include "serialio.asl" -/* SMBus 0:1f.3 */ +/* SMBus 0:1f.4 */ #include "smbus.asl" /* USB XHCI 0:14.0 */ |