Consolidate reset API, add generic reset_prepare mechanism

There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.

This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).

Also remove cpu_reset() completely since it's not used anywhere and
doesn't seem very useful compared to the others.

Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19789
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

66 files changed, 181 insertions, 143 deletions

diff --git a/src/include/reset.h b/src/include/reset.h
index f7501b53daf0..934ed9b1fcef 100644
--- a/src/include/reset.h
+++ b/src/include/reset.h
@@ -1,15 +1,30 @@
 #ifndef RESET_H
 #define RESET_H
 
-#if CONFIG_HAVE_HARD_RESET
-void hard_reset(void);
-#else
-#define hard_reset() do {} while (0)
-#endif
-void soft_reset(void);
-void cpu_reset(void);
-/* Some Intel SoCs use a special reset that is specific to SoC */
-void global_reset(void);
-/* Some Intel SoCs may need to prepare/wait before reset */
-void reset_prepare(void);
+/* Generic reset functions. Call from code that wants to trigger a reset. */
+
+/* Super-hard reset specific to some Intel SoCs. */
+__attribute__((noreturn)) void global_reset(void);
+/* Full board reset. Resets SoC and most/all board components (e.g. DRAM). */
+__attribute__((noreturn)) void hard_reset(void);
+/* Board reset. Resets SoC some board components (e.g. TPM but not DRAM). */
+__attribute__((noreturn)) void soft_reset(void);
+
+/* Reset implementations. Implement these in SoC or mainboard code. Implement
+   at least hard_reset() if possible, others fall back to it if necessary. */
+void do_global_reset(void);
+void do_hard_reset(void);
+void do_soft_reset(void);
+
+enum reset_type {	/* listed in order of softness */
+	GLOBAL_RESET,
+	HARD_RESET,
+	SOFT_RESET,
+};
+
+/* Callback that an SoC may override to perform special actions before reset.
+   Take into account that softer resets may fall back to harder resets if not
+   implemented... this will *not* trigger another callback! */
+void soc_reset_prepare(enum reset_type reset_type);
+
 #endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index c4d4f6ab409c..5079bbfea5d0 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -223,6 +223,13 @@ romstage-y += halt.c
 ramstage-y += halt.c
 smm-y += halt.c
 
+bootblock-y += reset.c
+verstage-y += reset.c
+romstage-y += reset.c
+postcar-y += reset.c
+ramstage-y += reset.c
+smm-y += reset.c
+
 postcar-y += bootmode.c
 postcar-y += boot_device.c
 postcar-y += cbfs.c
diff --git a/src/lib/reset.c b/src/lib/reset.c
new file mode 100644
index 000000000000..703118a6f5c2
--- /dev/null
+++ b/src/lib/reset.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cache.h>
+#include <console/console.h>
+#include <halt.h>
+#include <reset.h>
+
+__attribute__((noreturn)) static void __hard_reset(void) {
+	if (IS_ENABLED(CONFIG_HAVE_HARD_RESET))
+		do_hard_reset();
+	else
+		printk(BIOS_CRIT, "No hard_reset implementation, hanging...\n");
+	halt();
+}
+
+/* Not all platforms implement all reset types. Fall back to hard_reset. */
+__attribute__((weak)) void do_global_reset(void) { __hard_reset(); }
+__attribute__((weak)) void do_soft_reset(void) { __hard_reset(); }
+
+__attribute__((weak)) void soc_reset_prepare(enum reset_type rt) { /* no-op */ }
+
+void global_reset(void)
+{
+	printk(BIOS_INFO, "%s() called!\n", __func__);
+	soc_reset_prepare(GLOBAL_RESET);
+	dcache_clean_all();
+	do_global_reset();
+	halt();
+}
+
+void hard_reset(void)
+{
+	printk(BIOS_INFO, "%s() called!\n", __func__);
+	soc_reset_prepare(HARD_RESET);
+	dcache_clean_all();
+	__hard_reset();
+}
+
+void soft_reset(void)
+{
+	printk(BIOS_INFO, "%s() called!\n", __func__);
+	soc_reset_prepare(SOFT_RESET);
+	dcache_clean_all();
+	do_soft_reset();
+	halt();
+}
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index 3601e50090c2..a19b46af26e7 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -55,7 +55,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 }
 
 #include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	uint8_t tmp;
 
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index fdb8577a7218..706b8592b519 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -55,7 +55,7 @@ int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	uint8_t tmp;
 
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index f1477c3e2e34..1df033ad9046 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -53,7 +53,7 @@ int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	uint8_t tmp;
 
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 7864f962741e..13113b401950 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -81,7 +81,7 @@ static void ldtstop_sb(void)
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	uint8_t tmp;
 
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 89948b7c7f9a..61d74886536a 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -64,7 +64,7 @@ int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	uint8_t tmp;
 
diff --git a/src/mainboard/google/foster/reset.c b/src/mainboard/google/foster/reset.c
index df16b78dae0e..1b9e9e9a3621 100644
--- a/src/mainboard/google/foster/reset.c
+++ b/src/mainboard/google/foster/reset.c
@@ -18,8 +18,7 @@
 #include <gpio.h>
 #include <reset.h>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	gpio_output(GPIO(I5), 0);
-	while(1);
 }
diff --git a/src/mainboard/google/gale/reset.c b/src/mainboard/google/gale/reset.c
index d37051a9cbae..23d83bfdf372 100644
--- a/src/mainboard/google/gale/reset.c
+++ b/src/mainboard/google/gale/reset.c
@@ -19,7 +19,7 @@
 #include <soc/iomap.h>
 #include <reset.h>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	/*
 	 * At boot time the boot loaders would have set a magic cookie
diff --git a/src/mainboard/google/gru/reset.c b/src/mainboard/google/gru/reset.c
index bd06923532a0..0311d587c690 100644
--- a/src/mainboard/google/gru/reset.c
+++ b/src/mainboard/google/gru/reset.c
@@ -18,9 +18,7 @@
 
 #include "board.h"
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	gpio_output(GPIO_RESET, 1);
-	while (1)
-		;
 }
diff --git a/src/mainboard/google/nyan/reset.c b/src/mainboard/google/nyan/reset.c
index 9612d56b3c68..ee36292f7027 100644
--- a/src/mainboard/google/nyan/reset.c
+++ b/src/mainboard/google/nyan/reset.c
@@ -17,8 +17,7 @@
 #include <gpio.h>
 #include <reset.h>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
         gpio_output(GPIO(I5), 0);
-        while(1);
 }
diff --git a/src/mainboard/google/nyan_big/reset.c b/src/mainboard/google/nyan_big/reset.c
index 9612d56b3c68..ee36292f7027 100644
--- a/src/mainboard/google/nyan_big/reset.c
+++ b/src/mainboard/google/nyan_big/reset.c
@@ -17,8 +17,7 @@
 #include <gpio.h>
 #include <reset.h>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
         gpio_output(GPIO(I5), 0);
-        while(1);
 }
diff --git a/src/mainboard/google/nyan_blaze/reset.c b/src/mainboard/google/nyan_blaze/reset.c
index 9612d56b3c68..ee36292f7027 100644
--- a/src/mainboard/google/nyan_blaze/reset.c
+++ b/src/mainboard/google/nyan_blaze/reset.c
@@ -17,8 +17,7 @@
 #include <gpio.h>
 #include <reset.h>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
         gpio_output(GPIO(I5), 0);
-        while(1);
 }
diff --git a/src/mainboard/google/purin/reset.c b/src/mainboard/google/purin/reset.c
index 549717502214..3667bbfa0762 100644
--- a/src/mainboard/google/purin/reset.c
+++ b/src/mainboard/google/purin/reset.c
@@ -15,8 +15,6 @@
 
 #include <reset.h>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
-	while (1)
-		;
 }
diff --git a/src/mainboard/google/rotor/reset.c b/src/mainboard/google/rotor/reset.c
index 37c2db7c19c3..fc97f2df685f 100644
--- a/src/mainboard/google/rotor/reset.c
+++ b/src/mainboard/google/rotor/reset.c
@@ -16,7 +16,7 @@
 #include <reset.h>
 #include <soc/reset.h>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	mvmap2315_reset();
 }
diff --git a/src/mainboard/google/smaug/reset.c b/src/mainboard/google/smaug/reset.c
index f87582901a4d..fc9a0b62145a 100644
--- a/src/mainboard/google/smaug/reset.c
+++ b/src/mainboard/google/smaug/reset.c
@@ -18,9 +18,7 @@
 
 #include "gpio.h"
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	gpio_output(AP_SYS_RESET_L, 0);
-	while (1)
-		;
 }
diff --git a/src/mainboard/google/storm/reset.c b/src/mainboard/google/storm/reset.c
index 94dcd4befd14..d8f25274b164 100644
--- a/src/mainboard/google/storm/reset.c
+++ b/src/mainboard/google/storm/reset.c
@@ -37,12 +37,9 @@ static void wdog_reset(void)
 	write32(APCS_WDT0_BITE_TIME, RESET_WDT_BITE_TIME);
 	write32(APCS_WDT0_EN, 1);
 	write32(APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE, 1);
-
-	for (;;)
-		;
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	wdog_reset();
 }
diff --git a/src/mainboard/google/veyron/reset.c b/src/mainboard/google/veyron/reset.c
index 0d11e76f707b..a937aff65e0e 100644
--- a/src/mainboard/google/veyron/reset.c
+++ b/src/mainboard/google/veyron/reset.c
@@ -19,8 +19,7 @@
 
 #include "board.h"
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	gpio_output(GPIO_RESET, 1);
-	while (1);
 }
diff --git a/src/mainboard/google/veyron_mickey/reset.c b/src/mainboard/google/veyron_mickey/reset.c
index 0d11e76f707b..a937aff65e0e 100644
--- a/src/mainboard/google/veyron_mickey/reset.c
+++ b/src/mainboard/google/veyron_mickey/reset.c
@@ -19,8 +19,7 @@
 
 #include "board.h"
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	gpio_output(GPIO_RESET, 1);
-	while (1);
 }
diff --git a/src/mainboard/google/veyron_rialto/reset.c b/src/mainboard/google/veyron_rialto/reset.c
index cf3a6d8a2fa5..a937aff65e0e 100644
--- a/src/mainboard/google/veyron_rialto/reset.c
+++ b/src/mainboard/google/veyron_rialto/reset.c
@@ -19,9 +19,7 @@
 
 #include "board.h"
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	gpio_output(GPIO_RESET, 1);
-	while (1)
-		;
 }
diff --git a/src/northbridge/via/cx700/reset.c b/src/northbridge/via/cx700/reset.c
index b3c2a658dbf4..8a627590b6cb 100644
--- a/src/northbridge/via/cx700/reset.c
+++ b/src/northbridge/via/cx700/reset.c
@@ -16,7 +16,7 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb((1 << 2) | (1 << 1), 0xcf9);
 }
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index fbb8fdf898db..36382934daf5 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -43,7 +43,7 @@ static uint64_t uma_memory_size = 0;
  * remapping mechanism will overflow, the effects of which are unknown.
  */
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb((1 << 2) | (1 << 1), 0xcf9);
 }
diff --git a/src/soc/dmp/vortex86ex/hard_reset.c b/src/soc/dmp/vortex86ex/hard_reset.c
index 9b9c42673315..fe127aab9128 100644
--- a/src/soc/dmp/vortex86ex/hard_reset.c
+++ b/src/soc/dmp/vortex86ex/hard_reset.c
@@ -16,6 +16,6 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 }
diff --git a/src/soc/imgtec/pistachio/reset.c b/src/soc/imgtec/pistachio/reset.c
index fc581df98ef7..c0e9105abfb4 100644
--- a/src/soc/imgtec/pistachio/reset.c
+++ b/src/soc/imgtec/pistachio/reset.c
@@ -20,7 +20,7 @@
 #define PISTACHIO_WD_ADDR		0xB8102100
 #define PISTACHIO_WD_SW_RST_OFFSET	0x0000
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	/* Generate system reset */
 	write32(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1);
diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c
index 56273cc03e8b..15e78fe203d8 100644
--- a/src/soc/intel/apollolake/reset.c
+++ b/src/soc/intel/apollolake/reset.c
@@ -23,13 +23,13 @@
 
 #define CSE_WAIT_MAX_MS							1000
 
-void global_reset(void)
+void do_global_reset(void)
 {
 	global_reset_enable(1);
-	hard_reset();
+	do_hard_reset();
 }
 
-void reset_prepare(void)
+void soc_reset_prepare(enum reset_type reset_type)
 {
 	struct stopwatch sw;
 
diff --git a/src/soc/intel/baytrail/reset.c b/src/soc/intel/baytrail/reset.c
index fd38f612556b..e38a2e6ec8cf 100644
--- a/src/soc/intel/baytrail/reset.c
+++ b/src/soc/intel/baytrail/reset.c
@@ -29,13 +29,13 @@ void warm_reset(void)
 	outb(RST_CPU | SYS_RST, RST_CNT);
 }
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	/* Sends INIT# to CPU */
 	outb(RST_CPU, RST_CNT);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	/* Don't power cycle on hard_reset(). It's not really clear what the
 	 * semantics should be for the meaning of hard_reset(). */
diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c
index e4d01c279048..ad90dcd88061 100644
--- a/src/soc/intel/broadwell/reset.c
+++ b/src/soc/intel/broadwell/reset.c
@@ -28,12 +28,12 @@
  * with ETR[20] set.
  */
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	outb(0x04, 0xcf9);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb(0x06, 0xcf9);
 }
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
index e9be1855b032..06a534ce9993 100644
--- a/src/soc/intel/common/reset.c
+++ b/src/soc/intel/common/reset.c
@@ -25,39 +25,16 @@
 #define RST_CPU			(1 << 2)
 #define SYS_RST			(1 << 1)
 
-#ifdef __ROMCC__
-#define WEAK
-#else
-#define WEAK __attribute__((weak))
-#endif
-
-void WEAK reset_prepare(void) { /* do nothing */ }
-
 #if IS_ENABLED(CONFIG_HAVE_HARD_RESET)
-void hard_reset(void)
+void do_hard_reset(void)
 {
-	reset_prepare();
 	/* S0->S5->S0 trip. */
 	outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
-	while (1)
-		hlt();
 }
 #endif
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
-	reset_prepare();
 	/* PMC_PLTRST# asserted. */
 	outb(RST_CPU | SYS_RST, RST_CNT);
-	while (1)
-		hlt();
-}
-
-void cpu_reset(void)
-{
-	reset_prepare();
-	/* Sends INIT# to CPU */
-	outb(RST_CPU, RST_CNT);
-	while (1)
-		hlt();
 }
diff --git a/src/soc/intel/fsp_baytrail/reset.c b/src/soc/intel/fsp_baytrail/reset.c
index fd38f612556b..e38a2e6ec8cf 100644
--- a/src/soc/intel/fsp_baytrail/reset.c
+++ b/src/soc/intel/fsp_baytrail/reset.c
@@ -29,13 +29,13 @@ void warm_reset(void)
 	outb(RST_CPU | SYS_RST, RST_CNT);
 }
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	/* Sends INIT# to CPU */
 	outb(RST_CPU, RST_CNT);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	/* Don't power cycle on hard_reset(). It's not really clear what the
 	 * semantics should be for the meaning of hard_reset(). */
diff --git a/src/soc/intel/fsp_broadwell_de/reset.c b/src/soc/intel/fsp_broadwell_de/reset.c
index 7e1c582749ad..78d74939e33e 100644
--- a/src/soc/intel/fsp_broadwell_de/reset.c
+++ b/src/soc/intel/fsp_broadwell_de/reset.c
@@ -23,7 +23,7 @@ void warm_reset(void)
     outb(0x06, 0xcf9);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	warm_reset();
 }
diff --git a/src/soc/intel/sch/reset.c b/src/soc/intel/sch/reset.c
index 2574565f7513..91bcd690ca68 100644
--- a/src/soc/intel/sch/reset.c
+++ b/src/soc/intel/sch/reset.c
@@ -17,12 +17,12 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	outb(0x04, 0xcf9);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb(0x02, 0xcf9);
 	outb(0x06, 0xcf9);
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
index 69109145f26f..dee98a4c1ecf 100644
--- a/src/soc/intel/skylake/reset.c
+++ b/src/soc/intel/skylake/reset.c
@@ -41,7 +41,7 @@ static void do_force_global_reset(void)
 	hard_reset();
 }
 
-void global_reset(void)
+void do_global_reset(void)
 {
 	if (send_global_reset() != 0) {
 		/* If ME unable to reset platform then
diff --git a/src/soc/mediatek/mt8173/wdt.c b/src/soc/mediatek/mt8173/wdt.c
index 93ffe09209c4..22f1c87ac5c4 100644
--- a/src/soc/mediatek/mt8173/wdt.c
+++ b/src/soc/mediatek/mt8173/wdt.c
@@ -57,10 +57,7 @@ int mtk_wdt_init(void)
 	return wdt_sta;
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	write32(&mt8173_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
-
-	while (1)
-		;
 }
diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c
index f27650dae69c..de99a823217c 100644
--- a/src/soc/samsung/exynos5250/power.c
+++ b/src/soc/samsung/exynos5250/power.c
@@ -39,7 +39,7 @@ void power_reset(void)
 	setbits_le32(&exynos_power->sw_reset, 1);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	power_reset();
 }
diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c
index 200ec14c2ee1..e3f36f33099e 100644
--- a/src/southbridge/amd/agesa/hudson/reset.c
+++ b/src/southbridge/amd/agesa/hudson/reset.c
@@ -21,7 +21,7 @@
 
 #include <northbridge/amd/amdk8/reset_test.c>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 	/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c
index f451003aee26..2161669f4fde 100644
--- a/src/southbridge/amd/amd8111/early_ctrl.c
+++ b/src/southbridge/amd/amd8111/early_ctrl.c
@@ -38,7 +38,7 @@ static void enable_cf9(void)
 	enable_cf9_x(sbbusn, sbdn);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 	/* reset */
@@ -71,7 +71,7 @@ static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
 
 }
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 
 	unsigned sblk = get_sblk();
diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c
index fd2c82ab5b89..fea8891a9887 100644
--- a/src/southbridge/amd/amd8111/reset.c
+++ b/src/southbridge/amd/amd8111/reset.c
@@ -37,7 +37,7 @@ static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus)
 
 #include "../../../northbridge/amd/amdk8/reset_test.c"
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	pci_devfn_t dev;
 	unsigned bus;
diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c
index a5c42b72c9a8..40e861c215f2 100644
--- a/src/southbridge/amd/cimx/sb700/reset.c
+++ b/src/southbridge/amd/cimx/sb700/reset.c
@@ -40,7 +40,7 @@ static inline void set_bios_reset(void)
 	}
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 	/* Try rebooting through port 0xcf9 */
@@ -50,7 +50,7 @@ void hard_reset(void)
 }
 
 //SbReset();
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	set_bios_reset();
 	/* link reset */
diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c
index a5c42b72c9a8..40e861c215f2 100644
--- a/src/southbridge/amd/cimx/sb800/reset.c
+++ b/src/southbridge/amd/cimx/sb800/reset.c
@@ -40,7 +40,7 @@ static inline void set_bios_reset(void)
 	}
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 	/* Try rebooting through port 0xcf9 */
@@ -50,7 +50,7 @@ void hard_reset(void)
 }
 
 //SbReset();
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	set_bios_reset();
 	/* link reset */
diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c
index a5c42b72c9a8..40e861c215f2 100644
--- a/src/southbridge/amd/cimx/sb900/reset.c
+++ b/src/southbridge/amd/cimx/sb900/reset.c
@@ -40,7 +40,7 @@ static inline void set_bios_reset(void)
 	}
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 	/* Try rebooting through port 0xcf9 */
@@ -50,7 +50,7 @@ void hard_reset(void)
 }
 
 //SbReset();
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	set_bios_reset();
 	/* link reset */
diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c
index 200ec14c2ee1..e3f36f33099e 100644
--- a/src/southbridge/amd/pi/hudson/reset.c
+++ b/src/southbridge/amd/pi/hudson/reset.c
@@ -21,7 +21,7 @@
 
 #include <northbridge/amd/amdk8/reset_test.c>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 	/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c
index 2445310e6e24..f68bfd51ee51 100644
--- a/src/southbridge/amd/sb600/early_setup.c
+++ b/src/southbridge/amd/sb600/early_setup.c
@@ -173,7 +173,7 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
 	}
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 
@@ -182,7 +182,7 @@ void hard_reset(void)
 	outb(0x0e, 0x0cf9);
 }
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	set_bios_reset();
 	/* link reset */
diff --git a/src/southbridge/amd/sb600/reset.c b/src/southbridge/amd/sb600/reset.c
index beb35d11b1fd..04bf3f4e83c4 100644
--- a/src/southbridge/amd/sb600/reset.c
+++ b/src/southbridge/amd/sb600/reset.c
@@ -21,7 +21,7 @@
 
 #include <northbridge/amd/amdk8/reset_test.c>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 	/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
index 3c44982e6ab7..08780399b132 100644
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
@@ -44,7 +44,7 @@ static void set_bios_reset(void)
 	}
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 
@@ -56,7 +56,7 @@ void hard_reset(void)
 	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
 }
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	set_bios_reset();
 	/* link reset */
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index c9ae08c7551f..9ac66fb45d59 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -220,7 +220,7 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
 	pmio_write(0x81, byte);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 
@@ -229,7 +229,7 @@ void hard_reset(void)
 	outb(0x0e, 0x0cf9);
 }
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	set_bios_reset();
 	/* link reset */
diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c
index 200ec14c2ee1..e3f36f33099e 100644
--- a/src/southbridge/amd/sb800/reset.c
+++ b/src/southbridge/amd/sb800/reset.c
@@ -21,7 +21,7 @@
 
 #include <northbridge/amd/amdk8/reset_test.c>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 	/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
index 6ee4f6b85660..72354440c9f0 100644
--- a/src/southbridge/broadcom/bcm5785/early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/early_setup.c
@@ -105,7 +105,7 @@ void ldtstop_sb(void)
 }
 
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	bcm5785_enable_wdt_port_cf9();
 
@@ -116,7 +116,7 @@ void hard_reset(void)
 	outb(0x0e, 0x0cf9);
 }
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	bcm5785_enable_wdt_port_cf9();
 
diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c
index 7511d29ed55d..1041aae301c4 100644
--- a/src/southbridge/broadcom/bcm5785/reset.c
+++ b/src/southbridge/broadcom/bcm5785/reset.c
@@ -21,7 +21,7 @@
 
 #include "../../../northbridge/amd/amdk8/reset_test.c"
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 	/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c
index 804fb8137c7c..7faadb62df96 100644
--- a/src/southbridge/intel/bd82x6x/reset.c
+++ b/src/southbridge/intel/bd82x6x/reset.c
@@ -17,12 +17,12 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	outb(0x04, 0xcf9);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb(0x06, 0xcf9);
 }
diff --git a/src/southbridge/intel/fsp_bd82x6x/reset.c b/src/southbridge/intel/fsp_bd82x6x/reset.c
index a2e8236dc574..b1468da64bfc 100644
--- a/src/southbridge/intel/fsp_bd82x6x/reset.c
+++ b/src/southbridge/intel/fsp_bd82x6x/reset.c
@@ -18,12 +18,12 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	outb(0x04, 0xcf9);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb(0x06, 0xcf9);
 }
diff --git a/src/southbridge/intel/fsp_i89xx/reset.c b/src/southbridge/intel/fsp_i89xx/reset.c
index a2e8236dc574..b1468da64bfc 100644
--- a/src/southbridge/intel/fsp_i89xx/reset.c
+++ b/src/southbridge/intel/fsp_i89xx/reset.c
@@ -18,12 +18,12 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	outb(0x04, 0xcf9);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb(0x06, 0xcf9);
 }
diff --git a/src/southbridge/intel/fsp_rangeley/reset.c b/src/southbridge/intel/fsp_rangeley/reset.c
index 298dbce4b025..10b82ff4e571 100644
--- a/src/southbridge/intel/fsp_rangeley/reset.c
+++ b/src/southbridge/intel/fsp_rangeley/reset.c
@@ -18,12 +18,12 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	hard_reset();
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb(0x02, 0xcf9);
 	outb(0x06, 0xcf9);
diff --git a/src/southbridge/intel/i3100/reset.c b/src/southbridge/intel/i3100/reset.c
index 595bed3bacb8..af000e3e6629 100644
--- a/src/southbridge/intel/i3100/reset.c
+++ b/src/southbridge/intel/i3100/reset.c
@@ -17,7 +17,7 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb(0x06, 0xcf9);
 }
diff --git a/src/southbridge/intel/i82801ax/reset.c b/src/southbridge/intel/i82801ax/reset.c
index 74be595e9948..25254ca929bb 100644
--- a/src/southbridge/intel/i82801ax/reset.c
+++ b/src/southbridge/intel/i82801ax/reset.c
@@ -17,7 +17,7 @@
 #include <reset.h>
 #include <arch/io.h>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	/* Try rebooting through port 0xcf9. */
 	outb((1 << 2) | (1 << 1), 0xcf9);
diff --git a/src/southbridge/intel/i82801bx/reset.c b/src/southbridge/intel/i82801bx/reset.c
index 4a82b358639b..41b99c704d6e 100644
--- a/src/southbridge/intel/i82801bx/reset.c
+++ b/src/southbridge/intel/i82801bx/reset.c
@@ -17,7 +17,7 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	/* Try rebooting through port 0xcf9. */
 	outb((1 << 2) | (1 << 1), 0xcf9);
diff --git a/src/southbridge/intel/i82801dx/reset.c b/src/southbridge/intel/i82801dx/reset.c
index a6db91c7ba28..1839ad6f9a26 100644
--- a/src/southbridge/intel/i82801dx/reset.c
+++ b/src/southbridge/intel/i82801dx/reset.c
@@ -16,7 +16,7 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	/* Try rebooting through port 0xcf9 */
 	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
diff --git a/src/southbridge/intel/i82801gx/reset.c b/src/southbridge/intel/i82801gx/reset.c
index 97b82251f09d..e18f3e8ddc8c 100644
--- a/src/southbridge/intel/i82801gx/reset.c
+++ b/src/southbridge/intel/i82801gx/reset.c
@@ -17,20 +17,20 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	outb(0x04, 0xcf9);
 }
 
 #if 0
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	/* Try rebooting through port 0xcf9. */
 	outb((1 << 2) | (1 << 1), 0xcf9);
 }
 #endif
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb(0x02, 0xcf9);
 	outb(0x06, 0xcf9);
diff --git a/src/southbridge/intel/lynxpoint/reset.c b/src/southbridge/intel/lynxpoint/reset.c
index 804fb8137c7c..7faadb62df96 100644
--- a/src/southbridge/intel/lynxpoint/reset.c
+++ b/src/southbridge/intel/lynxpoint/reset.c
@@ -17,12 +17,12 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	outb(0x04, 0xcf9);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb(0x06, 0xcf9);
 }
diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c
index 1d4999ccbce8..79c9eff05037 100644
--- a/src/southbridge/nvidia/ck804/early_setup.c
+++ b/src/southbridge/nvidia/ck804/early_setup.c
@@ -310,7 +310,7 @@ static int ck804_early_setup_x(void)
 	return set_ht_link_ck804(4);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 
@@ -319,7 +319,7 @@ void hard_reset(void)
 	outb(0x0e, 0x0cf9);
 }
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	set_bios_reset();
 
diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c
index 689f98985fa6..aeea41b5514b 100644
--- a/src/southbridge/nvidia/ck804/early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/early_setup_car.c
@@ -357,7 +357,7 @@ static int ck804_early_setup_x(void)
 	return set_ht_link_ck804(4);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 
@@ -366,7 +366,7 @@ void hard_reset(void)
 	outb(0x0e, 0x0cf9);
 }
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	set_bios_reset();
 
diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c
index ad994dedc48f..bcb6dfc8f8d3 100644
--- a/src/southbridge/nvidia/ck804/reset.c
+++ b/src/southbridge/nvidia/ck804/reset.c
@@ -21,7 +21,7 @@
 
 #include "../../../northbridge/amd/amdk8/reset_test.c"
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 	/* Try rebooting through port 0xcf9. */
diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c
index 1f80316b8fde..cb3e2f0ae518 100644
--- a/src/southbridge/nvidia/mcp55/early_ctrl.c
+++ b/src/southbridge/nvidia/mcp55/early_ctrl.c
@@ -25,7 +25,7 @@
 #endif
 #include "mcp55.h"
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	set_bios_reset();
 	/* link reset */
@@ -33,7 +33,7 @@ void soft_reset(void)
 	outb(0x06, 0x0cf9);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 
diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c
index a381cd31a997..7be98d7a2f1c 100644
--- a/src/southbridge/nvidia/mcp55/reset.c
+++ b/src/southbridge/nvidia/mcp55/reset.c
@@ -24,7 +24,7 @@
 
 #include "../../../northbridge/amd/amdk8/reset_test.c"
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 	/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c
index 74ae1fa05a31..4fb2d9d11ba7 100644
--- a/src/southbridge/sis/sis966/early_ctrl.c
+++ b/src/southbridge/sis/sis966/early_ctrl.c
@@ -29,7 +29,7 @@ static unsigned get_sbdn(unsigned bus)
 	return (dev>>15) & 0x1f;
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 
@@ -44,7 +44,7 @@ static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
 	/* set VFSMAF ( VID/FID System Management Action Field) to 2 */
 }
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	set_bios_reset();
 
diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c
index a381cd31a997..7be98d7a2f1c 100644
--- a/src/southbridge/sis/sis966/reset.c
+++ b/src/southbridge/sis/sis966/reset.c
@@ -24,7 +24,7 @@
 
 #include "../../../northbridge/amd/amdk8/reset_test.c"
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	set_bios_reset();
 	/* Try rebooting through port 0xcf9 */