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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-04-13 19:40:06 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-14 18:45:13 +0000 |
| commit | 151cc6c14bd758ea6f9691f79792d33adce60698 (patch) | |
| tree | b047b9c96fd3d63f7d5d0e530aa963991176b6f4 | |
| parent | 7cc502b07a97c613be67daab7e8ab1ecfd70d544 (diff) | |
| download | coreboot-151cc6c14bd758ea6f9691f79792d33adce60698.tar.gz coreboot-151cc6c14bd758ea6f9691f79792d33adce60698.tar.bz2 coreboot-151cc6c14bd758ea6f9691f79792d33adce60698.zip | |
soc/amd/common/block/pm: remove POWER_STATE_DEFAULT_ON_AFTER_FAILURE
Not selecting POWER_STATE_DEFAULT_ON_AFTER_FAILURE brings Cezanne that
is currently the only SoC using this functionality in line with Picasso
where the default is that the board remains in power off mode after
power was lost and later restored. Boards can change this behavior by
selecting POWER_STATE_OFF_AFTER_FAILURE, POWER_STATE_ON_AFTER_FAILURE or
POWER_STATE_PREVIOUS_AFTER_FAILURE.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic96f40e3c9867cd821e58d752f58b763930f6d0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/soc/amd/common/block/pm/Kconfig | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/amd/common/block/pm/Kconfig b/src/soc/amd/common/block/pm/Kconfig index ebd1679ce620..538301de321f 100644 --- a/src/soc/amd/common/block/pm/Kconfig +++ b/src/soc/amd/common/block/pm/Kconfig @@ -8,9 +8,6 @@ config SOC_AMD_COMMON_BLOCK_PM if SOC_AMD_COMMON_BLOCK_PM -config POWER_STATE_DEFAULT_ON_AFTER_FAILURE - default y - config SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE bool help |