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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2022-07-29 16:06:05 -0700
committerSubrata Banik <subratabanik@google.com>2022-08-05 17:48:03 +0000
commit15b439e264b4f72e307802d75b692ba0948294f9 (patch)
treea55093c1971e26b1b4208571a3ece41310866443
parent1adba03884f1f1471838548ec560c11e8f2cb84c (diff)
downloadcoreboot-15b439e264b4f72e307802d75b692ba0948294f9.tar.gz
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vc/intel/fsp/mtl: Update header files from 2253_00 to 2304_01
Update header files for FSP for Meteor Lake platform to version 2304_01, previous version being 2253_00. FSPM: 1. Removed CpuCrashLogDevice 2. Address offset changes FSPS: Includes below new UPDs 1. VpuEnable 2. SerialIoI3cMode 3. ThcAssignment 4. PchIshI3cEnable BUG=b:240665069 TEST=emerge-rex intel-mtlfsp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I9740e5877af745124d573425da623e814d8df5d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66289 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h958
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h969
2 files changed, 977 insertions, 950 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
index 14975351e8a..8a2347ecd49 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
@@ -72,11 +72,9 @@ typedef struct {
**/
UINT8 EnableAbove4GBMmio;
-/** Offset 0x004B - Enable/Disable CrashLog Device 10
- Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog
- $EN_DIS
+/** Offset 0x004B - Reserved
**/
- UINT8 CpuCrashLogDevice;
+ UINT8 Reserved0;
/** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
@@ -282,7 +280,7 @@ typedef struct {
/** Offset 0x012D - Reserved
**/
- UINT8 Reserved0[3];
+ UINT8 Reserved1[3];
/** Offset 0x0130 - Tseg Size
Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
@@ -334,7 +332,7 @@ typedef struct {
/** Offset 0x014A - Reserved
**/
- UINT8 Reserved1;
+ UINT8 Reserved2;
/** Offset 0x014B - DCI DbC Mode
Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both:
@@ -352,7 +350,7 @@ typedef struct {
/** Offset 0x014D - Reserved
**/
- UINT8 Reserved2[6];
+ UINT8 Reserved3[6];
/** Offset 0x0153 - PCH Trace Hub Mode
Enable/Disable PCH TraceHub
@@ -384,7 +382,7 @@ typedef struct {
/** Offset 0x0158 - Reserved
**/
- UINT8 Reserved3[4];
+ UINT8 Reserved4[4];
/** Offset 0x015C - HD Audio DMIC Link Clock Select
Determines DMIC<N> Clock Source. 0: Both, 1: ClkA, 2: ClkB
@@ -452,7 +450,7 @@ typedef struct {
/** Offset 0x018A - Reserved
**/
- UINT8 Reserved4[2];
+ UINT8 Reserved5[2];
/** Offset 0x018C - DDR Frequency Limit
Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
@@ -469,7 +467,7 @@ typedef struct {
/** Offset 0x018F - Reserved
**/
- UINT8 Reserved5;
+ UINT8 Reserved6;
/** Offset 0x0190 - Memory Test on Warm Boot
Run Base Memory Test on Warm Boot
@@ -548,7 +546,7 @@ typedef struct {
/** Offset 0x019C - Reserved
**/
- UINT8 Reserved6[2];
+ UINT8 Reserved7[2];
/** Offset 0x019E - Memory Reference Clock
100MHz, 133MHz.
@@ -558,7 +556,7 @@ typedef struct {
/** Offset 0x019F - Reserved
**/
- UINT8 Reserved7;
+ UINT8 Reserved8;
/** Offset 0x01A0 - Memory Vdd Voltage
DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM
@@ -570,7 +568,7 @@ typedef struct {
/** Offset 0x01A2 - Reserved
**/
- UINT8 Reserved8[4];
+ UINT8 Reserved9[4];
/** Offset 0x01A6 - Memory Ratio
Automatic or the frequency will equal ratio times reference clock. Set to Auto to
@@ -611,7 +609,7 @@ typedef struct {
/** Offset 0x01AF - Reserved
**/
- UINT8 Reserved9;
+ UINT8 Reserved10;
/** Offset 0x01B0 - tREFI
Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
@@ -653,7 +651,7 @@ typedef struct {
/** Offset 0x01B8 - Reserved
**/
- UINT8 Reserved10[11];
+ UINT8 Reserved11[11];
/** Offset 0x01C3 - NMode
System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
@@ -689,30 +687,30 @@ typedef struct {
/** Offset 0x01D3 - Reserved
**/
- UINT8 Reserved11[63];
+ UINT8 Reserved12[67];
-/** Offset 0x0212 - MMIO size adjustment for AUTO mode
+/** Offset 0x0216 - MMIO size adjustment for AUTO mode
Positive number means increasing MMIO size, Negative value means decreasing MMIO
size: 0 (Default)=no change to AUTO mode MMIO size
**/
UINT16 MmioSizeAdjustment;
-/** Offset 0x0214 - Selection of the primary display device
+/** Offset 0x0218 - Selection of the primary display device
0=iGFX, 3(Default)=AUTO, 4=Hybrid Graphics
0:iGFX, 3:AUTO, 4:Hybrid Graphics
**/
UINT8 PrimaryDisplay;
-/** Offset 0x0215 - Reserved
+/** Offset 0x0219 - Reserved
**/
- UINT8 Reserved12[3];
+ UINT8 Reserved13[3];
-/** Offset 0x0218 - Temporary MMIO address for GMADR
+/** Offset 0x021C - Temporary MMIO address for GMADR
Obsolete field now and it has been extended to 64 bit address, used LMemBar
**/
UINT32 GmAdr;
-/** Offset 0x021C - Temporary MMIO address for GTTMMADR
+/** Offset 0x0220 - Temporary MMIO address for GTTMMADR
The reference code will use this as Temporary MMIO address space to access GTTMMADR
Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
@@ -720,181 +718,181 @@ typedef struct {
**/
UINT32 GttMmAdr;
-/** Offset 0x0220 - Enable/Disable MRC TXT dependency
+/** Offset 0x0224 - Enable/Disable MRC TXT dependency
When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
$EN_DIS
**/
UINT8 TxtImplemented;
-/** Offset 0x0221 - Enable/Disable SA OcSupport
+/** Offset 0x0225 - Enable/Disable SA OcSupport
Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
$EN_DIS
**/
UINT8 SaOcSupport;
-/** Offset 0x0222 - GT slice Voltage Mode
+/** Offset 0x0226 - GT slice Voltage Mode
0(Default): Adaptive, 1: Override
0: Adaptive, 1: Override
**/
UINT8 GtVoltageMode;
-/** Offset 0x0223 - Maximum GTs turbo ratio override
+/** Offset 0x0227 - Maximum GTs turbo ratio override
0(Default)=Minimal/Auto, 60=Maximum
**/
UINT8 GtMaxOcRatio;
-/** Offset 0x0224 - The voltage offset applied to GT slice
+/** Offset 0x0228 - The voltage offset applied to GT slice
0(Default)=Minimal, 1000=Maximum
**/
UINT16 GtVoltageOffset;
-/** Offset 0x0226 - The GT slice voltage override which is applied to the entire range of GT frequencies
+/** Offset 0x022A - The GT slice voltage override which is applied to the entire range of GT frequencies
0(Default)=Minimal, 2000=Maximum
**/
UINT16 GtVoltageOverride;
-/** Offset 0x0228 - adaptive voltage applied during turbo frequencies
+/** Offset 0x022C - adaptive voltage applied during turbo frequencies
0(Default)=Minimal, 2000=Maximum
**/
UINT16 GtExtraTurboVoltage;
-/** Offset 0x022A - voltage offset applied to the SA
+/** Offset 0x022E - voltage offset applied to the SA
0(Default)=Minimal, 1000=Maximum
**/
UINT16 SaVoltageOffset;
-/** Offset 0x022C - PCIe root port Function number for Hybrid Graphics dGPU
+/** Offset 0x0230 - PCIe root port Function number for Hybrid Graphics dGPU
Root port Index number to indicate which PCIe root port has dGPU
**/
UINT8 RootPortIndex;
-/** Offset 0x022D - Realtime Memory Timing
+/** Offset 0x0231 - Realtime Memory Timing
0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
realtime memory timing changes after MRC_DONE.
0: Disabled, 1: Enabled
**/
UINT8 RealtimeMemoryTiming;
-/** Offset 0x022E - This is policy to control iTBT PCIe Multiple Segment setting.
+/** Offset 0x0232 - This is policy to control iTBT PCIe Multiple Segment setting.
DEPRECATED
$EN_DIS
**/
UINT8 PcieMultipleSegmentEnabled;
-/** Offset 0x022F - Enable/Disable SA IPU
+/** Offset 0x0233 - Enable/Disable SA IPU
Enable(Default): Enable SA IPU, Disable: Disable SA IPU
$EN_DIS
**/
UINT8 SaIpuEnable;
-/** Offset 0x0230 - IMGU CLKOUT Configuration
+/** Offset 0x0234 - IMGU CLKOUT Configuration
The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
$EN_DIS
**/
UINT8 ImguClkOutEn[6];
-/** Offset 0x0236 - Program GPIOs for LFP on DDI port-A device
+/** Offset 0x023A - Program GPIOs for LFP on DDI port-A device
0=Disabled,1(Default)=eDP, 2=MIPI DSI
0:Disabled, 1:eDP, 2:MIPI DSI
**/
UINT8 DdiPortAConfig;
-/** Offset 0x0237 - Program GPIOs for LFP on DDI port-B device
+/** Offset 0x023B - Program GPIOs for LFP on DDI port-B device
0(Default)=Disabled,1=eDP, 2=MIPI DSI
0:Disabled, 1:eDP, 2:MIPI DSI
**/
UINT8 DdiPortBConfig;
-/** Offset 0x0238 - Enable or disable HPD of DDI port A
+/** Offset 0x023C - Enable or disable HPD of DDI port A
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortAHpd;
-/** Offset 0x0239 - Enable or disable HPD of DDI port B
+/** Offset 0x023D - Enable or disable HPD of DDI port B
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortBHpd;
-/** Offset 0x023A - Enable or disable HPD of DDI port C
+/** Offset 0x023E - Enable or disable HPD of DDI port C
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortCHpd;
-/** Offset 0x023B - Enable or disable HPD of DDI port 1
+/** Offset 0x023F - Enable or disable HPD of DDI port 1
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPort1Hpd;
-/** Offset 0x023C - Enable or disable HPD of DDI port 2
+/** Offset 0x0240 - Enable or disable HPD of DDI port 2
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort2Hpd;
-/** Offset 0x023D - Enable or disable HPD of DDI port 3
+/** Offset 0x0241 - Enable or disable HPD of DDI port 3
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort3Hpd;
-/** Offset 0x023E - Enable or disable HPD of DDI port 4
+/** Offset 0x0242 - Enable or disable HPD of DDI port 4
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort4Hpd;
-/** Offset 0x023F - Enable or disable DDC of DDI port A
+/** Offset 0x0243 - Enable or disable DDC of DDI port A
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortADdc;
-/** Offset 0x0240 - Enable or disable DDC of DDI port B
+/** Offset 0x0244 - Enable or disable DDC of DDI port B
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortBDdc;
-/** Offset 0x0241 - Enable or disable DDC of DDI port C
+/** Offset 0x0245 - Enable or disable DDC of DDI port C
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortCDdc;
-/** Offset 0x0242 - Enable DDC setting of DDI Port 1
+/** Offset 0x0246 - Enable DDC setting of DDI Port 1
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort1Ddc;
-/** Offset 0x0243 - Enable DDC setting of DDI Port 2
+/** Offset 0x0247 - Enable DDC setting of DDI Port 2
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort2Ddc;
-/** Offset 0x0244 - Enable DDC setting of DDI Port 3
+/** Offset 0x0248 - Enable DDC setting of DDI Port 3
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort3Ddc;
-/** Offset 0x0245 - Enable DDC setting of DDI Port 4
+/** Offset 0x0249 - Enable DDC setting of DDI Port 4
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort4Ddc;
-/** Offset 0x0246 - Reserved
+/** Offset 0x024A - Reserved
**/
- UINT8 Reserved13[10];
+ UINT8 Reserved14[14];
-/** Offset 0x0250 - Per-core HT Disable
+/** Offset 0x0258 - Per-core HT Disable
Defines the per-core HT disable mask where: 1 - Disable selected logical core HT,
0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value
of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have
@@ -902,7 +900,7 @@ typedef struct {
**/
UINT16 PerCoreHtDisable;
-/** Offset 0x0252 - Thermal Velocity Boost Ratio clipping
+/** Offset 0x025A - Thermal Velocity Boost Ratio clipping
0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction
caused by high package temperatures for processors that implement the Intel Thermal
Velocity Boost (TVB) feature
@@ -910,32 +908,32 @@ typedef struct {
**/
UINT8 TvbRatioClipping;
-/** Offset 0x0253 - Thermal Velocity Boost voltage optimization
+/** Offset 0x025B - Thermal Velocity Boost voltage optimization
0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations
for processors that implement the Intel Thermal Velocity Boost (TVB) feature.
$EN_DIS
**/
UINT8 TvbVoltageOptimization;
-/** Offset 0x0254 - Reserved
+/** Offset 0x025C - Reserved
**/
- UINT8 Reserved14[54];
+ UINT8 Reserved15[50];
-/** Offset 0x028A - DMI Max Link Speed
+/** Offset 0x028E - DMI Max Link Speed
Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
**/
UINT8 DmiMaxLinkSpeed;
-/** Offset 0x028B - DMI Equalization Phase 2
+/** Offset 0x028F - DMI Equalization Phase 2
DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
AUTO - Use the current default method
0:Disable phase2, 1:Enable phase2, 2:Auto
**/
UINT8 DmiGen3EqPh2Enable;
-/** Offset 0x028C - DMI Gen3 Equalization Phase3
+/** Offset 0x0290 - DMI Gen3 Equalization Phase3
DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
@@ -945,56 +943,56 @@ typedef struct {
**/
UINT8 DmiGen3EqPh3Method;
-/** Offset 0x028D - Enable/Disable DMI GEN3 Static EQ Phase1 programming
+/** Offset 0x0291 - Enable/Disable DMI GEN3 Static EQ Phase1 programming
Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
$EN_DIS
**/
UINT8 DmiGen3ProgramStaticEq;
-/** Offset 0x028E - DMI Gen3 Root port preset values per lane
+/** Offset 0x0292 - DMI Gen3 Root port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane
**/
UINT8 DmiGen3RootPortPreset[8];
-/** Offset 0x0296 - DMI Gen3 End port preset values per lane
+/** Offset 0x029A - DMI Gen3 End port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
**/
UINT8 DmiGen3EndPointPreset[8];
-/** Offset 0x029E - DMI Gen3 End port Hint values per lane
+/** Offset 0x02A2 - DMI Gen3 End port Hint values per lane
Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
**/
UINT8 DmiGen3EndPointHint[8];
-/** Offset 0x02A6 - DMI ASPM Configuration:{Combo
+/** Offset 0x02AA - DMI ASPM Configuration:{Combo
Set ASPM Configuration
0:Disabled, 1:L0s, 2:L1, 3:L1L0s
**/
UINT8 DmiAspm;
-/** Offset 0x02A7 - Enable/Disable DMI GEN3 Hardware Eq
+/** Offset 0x02AB - Enable/Disable DMI GEN3 Hardware Eq
Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0): Disable Hardware Eq, Enabled(0x1)(Default):
Enable EQ Phase1 Static Presets Programming
$EN_DIS
**/
UINT8 DmiHweq;
-/** Offset 0x02A8 - Enable/Disable DMI GEN3 Phase 23 Bypass
+/** Offset 0x02AC - Enable/Disable DMI GEN3 Phase 23 Bypass
DMIGEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1):
Enable Phase 23 Bypass
$EN_DIS
**/
UINT8 Gen3EqPhase23Bypass;
-/** Offset 0x02A9 - Enable/Disable DMI GEN3 Phase 3 Bypass
+/** Offset 0x02AD - Enable/Disable DMI GEN3 Phase 3 Bypass
DMIGEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1):
Enable Phase 3 Bypass
$EN_DIS
**/
UINT8 Gen3EqPhase3Bypass;
-/** Offset 0x02AA - Enable/Disable DMI Gen3 EQ Local Transmitter Coefficient Override Enable
+/** Offset 0x02AE - Enable/Disable DMI Gen3 EQ Local Transmitter Coefficient Override Enable
Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0): Disable Local
Transmitter Coefficient Override, Enabled(0x1)(Default): Enable Local Transmitter
Coefficient Override
@@ -1002,7 +1000,7 @@ typedef struct {
**/
UINT8 Gen3LtcoEnable;
-/** Offset 0x02AB - Enable/Disable DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable
+/** Offset 0x02AF - Enable/Disable DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable
Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default):
Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote
Transmitter Coefficient/Preset Override
@@ -1010,271 +1008,271 @@ typedef struct {
**/
UINT8 Gen3RtcoRtpoEnable;
-/** Offset 0x02AC - DMI Gen3 Transmitter Pre-Cursor Coefficient
+/** Offset 0x02B0 - DMI Gen3 Transmitter Pre-Cursor Coefficient
Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10,
2 is default for each lane
**/
UINT8 DmiGen3Ltcpre[8];
-/** Offset 0x02B4 - DMI Gen3 Transmitter Post-Cursor Coefficient
+/** Offset 0x02B8 - DMI Gen3 Transmitter Post-Cursor Coefficient
Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default
for each lane
**/
UINT8 DmiGen3Ltcpo[8];
-/** Offset 0x02BC - Reserved
+/** Offset 0x02C0 - Reserved
**/
- UINT8 Reserved15[16];
+ UINT8 Reserved16[16];
-/** Offset 0x02CC - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable
+/** Offset 0x02D0 - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable
Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable,
Manual(0x1): Enable DmiGen3DsPresetEnable
$EN_DIS
**/
UINT8 DmiGen3DsPresetEnable;
-/** Offset 0x02CD - DMI Gen3 Root port preset Rx values per lane
+/** Offset 0x02D1 - DMI Gen3 Root port preset Rx values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default
for each lane
**/
UINT8 DmiGen3DsPortRxPreset[8];
-/** Offset 0x02D5 - DMI Gen3 Root port preset Tx values per lane
+/** Offset 0x02D9 - DMI Gen3 Root port preset Tx values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default
for each lane
**/
UINT8 DmiGen3DsPortTxPreset[8];
-/** Offset 0x02DD - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable
+/** Offset 0x02E1 - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable
Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable,
Manual(0x1): Enable DmiGen3UsPresetEnable
$EN_DIS
**/
UINT8 DmiGen3UsPresetEnable;
-/** Offset 0x02DE - DMI Gen3 Root port preset Rx values per lane
+/** Offset 0x02E2 - DMI Gen3 Root port preset Rx values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default
for each lane
**/
UINT8 DmiGen3UsPortRxPreset[8];
-/** Offset 0x02E6 - DMI Gen3 Root port preset Tx values per lane
+/** Offset 0x02EA - DMI Gen3 Root port preset Tx values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default
for each lane
**/
UINT8 DmiGen3UsPortTxPreset[8];
-/** Offset 0x02EE - Reserved
+/** Offset 0x02F2 - Reserved
**/
- UINT8 Reserved16[54];
+ UINT8 Reserved17[54];
-/** Offset 0x0324 - DMI ASPM L1 exit Latency
+/** Offset 0x0328 - DMI ASPM L1 exit Latency
Range: 0-7, 4 is default L1 exit Latency
**/
UINT8 DmiAspmL1ExitLatency;
-/** Offset 0x0325 - Reserved
+/** Offset 0x0329 - Reserved
**/
- UINT8 Reserved17[39];
+ UINT8 Reserved18[39];
-/** Offset 0x034C - BIST on Reset
+/** Offset 0x0350 - BIST on Reset
Enable/Disable BIST (Built-In Self Test) on reset. <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 BistOnReset;
-/** Offset 0x034D - Skip Stop PBET Timer Enable/Disable
+/** Offset 0x0351 - Skip Stop PBET Timer Enable/Disable
Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 SkipStopPbet;
-/** Offset 0x034E - Over clocking support
+/** Offset 0x0352 - Over clocking support
Over clocking support; <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 OcSupport;
-/** Offset 0x034F - Over clocking Lock
+/** Offset 0x0353 - Over clocking Lock
Lock Overclocking. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 OcLock;
-/** Offset 0x0350 - Maximum Core Turbo Ratio Override
+/** Offset 0x0354 - Maximum Core Turbo Ratio Override
Maximum core turbo ratio override allows to increase CPU core frequency beyond the
fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85 if CoreRatioExtensionMode
is disabled. 0-120 if CoreRatioExtensionMode is enabled.
**/
UINT8 CoreMaxOcRatio;
-/** Offset 0x0351 - Core voltage mode
+/** Offset 0x0355 - Core voltage mode
Core voltage mode; <b>0: Adaptive</b>; 1: Override.
$EN_DIS
**/
UINT8 CoreVoltageMode;
-/** Offset 0x0352 - Maximum clr turbo ratio override
+/** Offset 0x0356 - Maximum clr turbo ratio override
Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85
**/
UINT8 RingMaxOcRatio;
-/** Offset 0x0353 - Hyper Threading Enable/Disable
+/** Offset 0x0357 - Hyper Threading Enable/Disable
Enable or Disable Hyper-Threading Technology. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 HyperThreading;
-/** Offset 0x0354 - Enable or Disable CPU Ratio Override
+/** Offset 0x0358 - Enable or Disable CPU Ratio Override
Enable/Disable CPU Flex Ratio Programming; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 CpuRatioOverride;
-/** Offset 0x0355 - CPU ratio value
+/** Offset 0x0359 - CPU ratio value
This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio
set by Hardware (HFM). Valid Range 0 to 63.
**/
UINT8 CpuRatio;
-/** Offset 0x0356 - Reserved
+/** Offset 0x035A - Reserved
**/
- UINT8 Reserved18;
+ UINT8 Reserved19;
-/** Offset 0x0357 - Number of active big cores
+/** Offset 0x035B - Number of active big cores
Number of P-cores to enable in each processor package. Note: Number of P-Cores and
E-Cores are looked at together. When both are {0,0
0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores
**/
UINT8 ActiveCoreCount;
-/** Offset 0x0358 - Processor Early Power On Configuration FCLK setting
+/** Offset 0x035C - Processor Early Power On Configuration FCLK setting
FCLK frequency can take values of 400MHz, 800MHz and 1GHz. <b>0: 800 MHz (ULT/ULX)</b>.
<b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved
0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
**/
UINT8 FClkFrequency;
-/** Offset 0x0359 - Enable or Disable VMX
+/** Offset 0x035D - Enable or Disable VMX
Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities
provided by Vanderpool Technology. 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 VmxEnable;
-/** Offset 0x035A - AVX2 Ratio Offset
+/** Offset 0x035E - AVX2 Ratio Offset
0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
**/
UINT8 Avx2RatioOffset;
-/** Offset 0x035B - AVX3 Ratio Offset
+/** Offset 0x035F - AVX3 Ratio Offset
0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
**/
UINT8 Avx3RatioOffset;
-/** Offset 0x035C - BCLK Adaptive Voltage Enable
+/** Offset 0x0360 - BCLK Adaptive Voltage Enable
When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
Disable;<b> 1: Enable
$EN_DIS
**/
UINT8 BclkAdaptiveVoltage;
-/** Offset 0x035D - Reserved
+/** Offset 0x0361 - Reserved
**/
- UINT8 Reserved19;
+ UINT8 Reserved20;
-/** Offset 0x035E - core voltage override
+/** Offset 0x0362 - core voltage override
The core voltage override which is applied to the entire range of cpu core frequencies.
Valid Range 0 to 2000
**/
UINT16 CoreVoltageOverride;
-/** Offset 0x0360 - Core Turbo voltage Adaptive
+/** Offset 0x0364 - Core Turbo voltage Adaptive
Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
Valid Range 0 to 2000
**/
UINT16 CoreVoltageAdaptive;
-/** Offset 0x0362 - Core Turbo voltage Offset
+/** Offset 0x0366 - Core Turbo voltage Offset
The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
**/
UINT16 CoreVoltageOffset;
-/** Offset 0x0364 - Core PLL voltage offset
+/** Offset 0x0368 - Core PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 CorePllVoltageOffset;
-/** Offset 0x0365 - Ring Downbin
+/** Offset 0x0369 - Ring Downbin
Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
lower than the core ratio.0: Disable; <b>1: Enable.</b>
$EN_DIS
**/
UINT8 RingDownBin;
-/** Offset 0x0366 - Ring voltage mode
+/** Offset 0x036A - Ring voltage mode
Ring voltage mode; <b>0: Adaptive</b>; 1: Override.
$EN_DIS
**/
UINT8 RingVoltageMode;
-/** Offset 0x0367 - TjMax Offset
+/** Offset 0x036B - TjMax Offset
TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
**/
UINT8 TjMaxOffset;
-/** Offset 0x0368 - Ring voltage override
+/** Offset 0x036C - Ring voltage override
The ring voltage override which is applied to the entire range of cpu ring frequencies.
Valid Range 0 to 2000
**/
UINT16 RingVoltageOverride;
-/** Offset 0x036A - Ring Turbo voltage Adaptive
+/** Offset 0x036E - Ring Turbo voltage Adaptive
Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.
Valid Range 0 to 2000
**/
UINT16 RingVoltageAdaptive;
-/** Offset 0x036C - Ring Turbo voltage Offset
+/** Offset 0x0370 - Ring Turbo voltage Offset
The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000
**/
UINT16 RingVoltageOffset;
-/** Offset 0x036E - Enable or Disable TME
+/** Offset 0x0372 - Enable or Disable TME
Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks.
<b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 TmeEnable;
-/** Offset 0x036F - Enable CPU CrashLog
+/** Offset 0x0373 - Enable CPU CrashLog
Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 CpuCrashLogEnable;
-/** Offset 0x0370 - CPU Run Control
+/** Offset 0x0374 - CPU Run Control
Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2:
No Change</b>
0:Disabled, 1:Enabled, 2:No Change
**/
UINT8 DebugInterfaceEnable;
-/** Offset 0x0371 - CPU Run Control Lock
+/** Offset 0x0375 - CPU Run Control Lock
Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 DebugInterfaceLockEnable;
-/** Offset 0x0372 - Reserved
+/** Offset 0x0376 - Reserved
**/
- UINT8 Reserved20[35];
+ UINT8 Reserved21[35];
-/** Offset 0x0395 - Core VF Point Offset Mode
+/** Offset 0x0399 - Core VF Point Offset Mode
Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes.
In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode,
setting a selected VF point; <b>0: Legacy</b>; 1: Selection.
@@ -1282,54 +1280,54 @@ typedef struct {
**/
UINT8 CoreVfPointOffsetMode;
-/** Offset 0x0396 - Core VF Point Offset
+/** Offset 0x039A - Core VF Point Offset
Array used to specifies the Core Voltage Offset applied to the each selected VF
Point. This voltage is specified in millivolts.
**/
UINT16 CoreVfPointOffset[15];
-/** Offset 0x03B4 - Core VF Point Offset Prefix
+/** Offset 0x03B8 - Core VF Point Offset Prefix
Sets the CoreVfPointOffset value as positive or negative for corresponding core
VF Point; <b>0: Positive </b>; 1: Negative.
0:Positive, 1:Negative
**/
UINT8 CoreVfPointOffsetPrefix[15];
-/** Offset 0x03C3 - Core VF Point Ratio
+/** Offset 0x03C7 - Core VF Point Ratio
Array for the each selected Core VF Point to display the ration.
**/
UINT8 CoreVfPointRatio[15];
-/** Offset 0x03D2 - Core VF Point Count
+/** Offset 0x03D6 - Core VF Point Count
Number of supported Core Voltage & Frequency Point Offset
**/
UINT8 CoreVfPointCount;
-/** Offset 0x03D3 - Reserved
+/** Offset 0x03D7 - Reserved
**/
- UINT8 Reserved21[25];
+ UINT8 Reserved22[25];
-/** Offset 0x03EC - Per Core Max Ratio override
+/** Offset 0x03F0 - Per Core Max Ratio override
Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
favored core ratio to each Core. <b>0: Disable</b>, 1: enable
$EN_DIS
**/
UINT8 PerCoreRatioOverride;
-/** Offset 0x03ED - Reserved
+/** Offset 0x03F1 - Reserved
**/
- UINT8 Reserved22[41];
+ UINT8 Reserved23[41];
-/** Offset 0x0416 - Per Core Current Max Ratio
+/** Offset 0x041A - Per Core Current Max Ratio
Array for the Per Core Max Ratio
**/
UINT8 PerCoreRatio[8];
-/** Offset 0x041E - Reserved
+/** Offset 0x0422 - Reserved
**/
- UINT8 Reserved23[9];
+ UINT8 Reserved24[9];
-/** Offset 0x0427 - Pvd Ratio Threshold for SOC/CPU die
+/** Offset 0x042B - Pvd Ratio Threshold for SOC/CPU die
Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio
(P0 to Pn) to select the multiplier so that the output is within the DCO frequency
range. As per the die selected, this threshold is applied to SA and MC/CMI PLL
@@ -1338,76 +1336,76 @@ typedef struct {
**/
UINT8 PvdRatioThreshold[2];
-/** Offset 0x0429 - Reserved
+/** Offset 0x042D - Reserved
**/
- UINT8 Reserved24[70];
+ UINT8 Reserved25[70];
-/** Offset 0x046F - BCLK Frequency Source
+/** Offset 0x0473 - BCLK Frequency Source
Clock source of BCLK OC frequency, <b>0:CPU BCLK</b>, 1:PCH BCLK, 2:External CLK
0:CPU BCLK, 1:PCH BCLK, 2:External CLK
**/
UINT8 BclkSource;
-/** Offset 0x0470 - GPIO Override
+/** Offset 0x0474 - GPIO Override
Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use
**/
UINT8 GpioOverride;
-/** Offset 0x0471 - Reserved
+/** Offset 0x0475 - Reserved
**/
- UINT8 Reserved25[3];
+ UINT8 Reserved26[3];
-/** Offset 0x0474 - CPU BCLK OC Frequency
+/** Offset 0x0478 - CPU BCLK OC Frequency
CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
40Mhz-1000Mhz.
**/
UINT32 CpuBclkOcFrequency;
-/** Offset 0x0478 - Reserved
+/** Offset 0x047C - Reserved
**/
- UINT8 Reserved26[4];
+ UINT8 Reserved27[4];
-/** Offset 0x047C - Enable CPU CrashLog GPRs dump
+/** Offset 0x0480 - Enable CPU CrashLog GPRs dump
Enable or Disable CPU CrashLog GPRs dump; <b>0: Disable</b>; 1: Enable; 2: Only
disable Smm GPRs dump
0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled
**/
UINT8 CrashLogGprs;
-/** Offset 0x047D - Reserved
+/** Offset 0x0481 - Reserved
**/
- UINT8 Reserved27[249];
+ UINT8 Reserved28[253];
-/** Offset 0x0576 - Thermal Design Current enable/disable
+/** Offset 0x057E - Thermal Design Current enable/disable
Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
[1] for GT, [2] for SA, [3] through [5] are Reserved.
**/
UINT8 TdcEnable[6];
-/** Offset 0x057C - Thermal Design Current time window
+/** Offset 0x0584 - Thermal Design Current time window
TDC Time Window, value of IA either in milliseconds or seconds, value of GT/SA is
in milliseconds. 1ms is default. Range of IA from 1ms to 448s, Range of GT/SA is
1ms to 10ms, except for 9ms. 9ms has no valid encoding in the MSR definition.
**/
UINT32 TdcTimeWindow[6];
-/** Offset 0x0594 - Reserved
+/** Offset 0x059C - Reserved
**/
- UINT8 Reserved28[181];
+ UINT8 Reserved29[204];
-/** Offset 0x0649 - BiosGuard
+/** Offset 0x0668 - BiosGuard
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
$EN_DIS
**/
UINT8 BiosGuard;
-/** Offset 0x064A
+/** Offset 0x0669
**/
UINT8 BiosGuardToolsInterface;
-/** Offset 0x064B - Txt
+/** Offset 0x066A - Txt
Enables utilization of additional hardware capabilities provided by Intel (R) Trusted
Execution Technology. Changes require a full power cycle to take effect. <b>0:
Disable</b>, 1: Enable
@@ -1415,1242 +1413,1246 @@ typedef struct {
**/
UINT8 Txt;
-/** Offset 0x064C - PrmrrSize
+/** Offset 0x066B - Reserved
+**/
+ UINT8 Reserved30;
+
+/** Offset 0x066C - PrmrrSize
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
**/
UINT32 PrmrrSize;
-/** Offset 0x0650 - SinitMemorySize
+/** Offset 0x0670 - SinitMemorySize
Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
**/
UINT32 SinitMemorySize;
-/** Offset 0x0654 - Reserved
+/** Offset 0x0674 - Reserved
**/
- UINT8 Reserved29[4];
+ UINT8 Reserved31[4];
-/** Offset 0x0658 - TxtDprMemoryBase
+/** Offset 0x0678 - TxtDprMemoryBase
Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
**/
UINT64 TxtDprMemoryBase;
-/** Offset 0x0660 - TxtHeapMemorySize
+/** Offset 0x0680 - TxtHeapMemorySize
Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
**/
UINT32 TxtHeapMemorySize;
-/** Offset 0x0664 - TxtDprMemorySize
+/** Offset 0x0684 - TxtDprMemorySize
Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize
, 1: enable
**/
UINT32 TxtDprMemorySize;
-/** Offset 0x0668 - BiosAcmBase
+/** Offset 0x0688 - BiosAcmBase
Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
**/
UINT32 BiosAcmBase;
-/** Offset 0x066C - BiosAcmSize
+/** Offset 0x068C - BiosAcmSize
Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
**/
UINT32 BiosAcmSize;
-/** Offset 0x0670 - ApStartupBase
+/** Offset 0x0690 - ApStartupBase
Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
**/
UINT32 ApStartupBase;
-/** Offset 0x0674 - TgaSize
+/** Offset 0x0694 - TgaSize
Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
**/
UINT32 TgaSize;
-/** Offset 0x0678 - TxtLcpPdBase
+/** Offset 0x0698 - TxtLcpPdBase
Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
**/
UINT64 TxtLcpPdBase;
-/** Offset 0x0680 - TxtLcpPdSize
+/** Offset 0x06A0 - TxtLcpPdSize
Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
**/
UINT64 TxtLcpPdSize;
-/** Offset 0x0688 - IsTPMPresence
+/** Offset 0x06A8 - IsTPMPresence
IsTPMPresence default values
**/
UINT8 IsTPMPresence;
-/** Offset 0x0689 - Reserved
+/** Offset 0x06A9 - Reserved
**/
- UINT8 Reserved30[32];
+ UINT8 Reserved32[32];
-/** Offset 0x06A9 - Enable PCH HSIO PCIE Rx Set Ctle
+/** Offset 0x06C9 - Enable PCH HSIO PCIE Rx Set Ctle
Enable PCH PCIe Gen 3 Set CTLE Value.
**/
UINT8 PchPcieHsioRxSetCtleEnable[28];
-/** Offset 0x06C5 - PCH HSIO PCIE Rx Set Ctle Value
+/** Offset 0x06E5 - PCH HSIO PCIE Rx Set Ctle Value
PCH PCIe Gen 3 Set CTLE Value.
**/
UINT8 PchPcieHsioRxSetCtle[28];
-/** Offset 0x06E1 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
+/** Offset 0x0701 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28];
-/** Offset 0x06FD - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x071D - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchPcieHsioTxGen1DownscaleAmp[28];
-/** Offset 0x0719 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
+/** Offset 0x0739 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28];
-/** Offset 0x0735 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0755 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchPcieHsioTxGen2DownscaleAmp[28];
-/** Offset 0x0751 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
+/** Offset 0x0771 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28];
-/** Offset 0x076D - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x078D - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchPcieHsioTxGen3DownscaleAmp[28];
-/** Offset 0x0789 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x07A9 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen1DeEmphEnable[28];
-/** Offset 0x07A5 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
+/** Offset 0x07C5 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchPcieHsioTxGen1DeEmph[28];
-/** Offset 0x07C1 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
+/** Offset 0x07E1 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28];
-/** Offset 0x07DD - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
+/** Offset 0x07FD - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
**/
UINT8 PchPcieHsioTxGen2DeEmph3p5[28];
-/** Offset 0x07F9 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
+/** Offset 0x0819 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28];
-/** Offset 0x0815 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
+/** Offset 0x0835 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
**/
UINT8 PchPcieHsioTxGen2DeEmph6p0[28];
-/** Offset 0x0831 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+/** Offset 0x0851 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];
-/** Offset 0x0839 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+/** Offset 0x0859 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
**/
UINT8 PchSataHsioRxGen1EqBoostMag[8];
-/** Offset 0x0841 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+/** Offset 0x0861 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];
-/** Offset 0x0849 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+/** Offset 0x0869 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
**/
UINT8 PchSataHsioRxGen2EqBoostMag[8];
-/** Offset 0x0851 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+/** Offset 0x0871 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];
-/** Offset 0x0859 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+/** Offset 0x0879 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
**/
UINT8 PchSataHsioRxGen3EqBoostMag[8];
-/** Offset 0x0861 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
+/** Offset 0x0881 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];
-/** Offset 0x0869 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0889 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchSataHsioTxGen1DownscaleAmp[8];
-/** Offset 0x0871 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+/** Offset 0x0891 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];
-/** Offset 0x0879 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0899 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchSataHsioTxGen2DownscaleAmp[8];
-/** Offset 0x0881 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+/** Offset 0x08A1 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];
-/** Offset 0x0889 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
+/** Offset 0x08A9 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchSataHsioTxGen3DownscaleAmp[8];
-/** Offset 0x0891 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x08B1 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen1DeEmphEnable[8];
-/** Offset 0x0899 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
+/** Offset 0x08B9 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchSataHsioTxGen1DeEmph[8];
-/** Offset 0x08A1 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x08C1 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen2DeEmphEnable[8];
-/** Offset 0x08A9 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
+/** Offset 0x08C9 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchSataHsioTxGen2DeEmph[8];
-/** Offset 0x08B1 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x08D1 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen3DeEmphEnable[8];
-/** Offset 0x08B9 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
+/** Offset 0x08D9 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchSataHsioTxGen3DeEmph[8];
-/** Offset 0x08C1 - PCH LPC Enhance the port 8xh decoding
+/** Offset 0x08E1 - PCH LPC Enhance the port 8xh decoding
Original LPC only decodes one byte of port 80h.
$EN_DIS
**/
UINT8 PchLpcEnhancePort8xhDecoding;
-/** Offset 0x08C2 - PCH Port80 Route
+/** Offset 0x08E2 - PCH Port80 Route
Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
$EN_DIS
**/
UINT8 PchPort80Route;
-/** Offset 0x08C3 - Enable SMBus ARP support
+/** Offset 0x08E3 - Enable SMBus ARP support
Enable SMBus ARP support.
$EN_DIS
**/
UINT8 SmbusArpEnable;
-/** Offset 0x08C4 - Number of RsvdSmbusAddressTable.
+/** Offset 0x08E4 - Number of RsvdSmbusAddressTable.
The number of elements in the RsvdSmbusAddressTable.
**/
UINT8 PchNumRsvdSmbusAddresses;
-/** Offset 0x08C5 - Reserved
+/** Offset 0x08E5 - Reserved
**/
- UINT8 Reserved31;
+ UINT8 Reserved33;
-/** Offset 0x08C6 - SMBUS Base Address
+/** Offset 0x08E6 - SMBUS Base Address
SMBUS Base Address (IO space).
**/
UINT16 PchSmbusIoBase;
-/** Offset 0x08C8 - Enable SMBus Alert Pin
+/** Offset 0x08E8 - Enable SMBus Alert Pin
Enable SMBus Alert Pin.
$EN_DIS
**/
UINT8 PchSmbAlertEnable;
-/** Offset 0x08C9 - Usage type for ClkSrc
+/** Offset 0x08E9 - Usage type for ClkSrc
0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used
**/
UINT8 PcieClkSrcUsage[18];
-/** Offset 0x08DB - Reserved
+/** Offset 0x08FB - Reserved
**/
- UINT8 Reserved32[14];
+ UINT8 Reserved34[14];
-/** Offset 0x08E9 - ClkReq-to-ClkSrc mapping
+/** Offset 0x0909 - ClkReq-to-ClkSrc mapping
Number of ClkReq signal assigned to ClkSrc
**/
UINT8 PcieClkSrcClkReq[18];
-/** Offset 0x08FB - Reserved
+/** Offset 0x091B - Reserved
**/
- UINT8 Reserved33[53];
+ UINT8 Reserved35[53];
-/** Offset 0x0930 - Enable PCIE RP Mask
+/** Offset 0x0950 - Enable PCIE RP Mask
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
for port1, bit1 for port2, and so on.
**/
UINT32 PcieRpEnableMask;
-/** Offset 0x0934 - VC Type
+/** Offset 0x0954 - VC Type
Virtual Channel Type Select: 0: VC0, 1: VC1.
0: VC0, 1: VC1
**/
UINT8 PchHdaVcType;
-/** Offset 0x0935 - Universal Audio Architecture compliance for DSP enabled system
+/** Offset 0x0955 - Universal Audio Architecture compliance for DSP enabled system
0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
driver or SST driver supported).
$EN_DIS
**/
UINT8 PchHdaDspUaaCompliance;
-/** Offset 0x0936 - Enable HD Audio Link
+/** Offset 0x0956 - Enable HD Audio Link
Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
$EN_DIS
**/
UINT8 PchHdaAudioLinkHdaEnable;
-/** Offset 0x0937 - Enable HDA SDI lanes
+/** Offset 0x0957 - Enable HDA SDI lanes
Enable/disable HDA SDI lanes.
**/
UINT8 PchHdaSdiEnable[2];
-/** Offset 0x0939 - HDA Power/Clock Gating (PGD/CGD)
+/** Offset 0x0959 - HDA Power/Clock Gating (PGD/CGD)
Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
FORCE_ENABLE, 2: FORCE_DISABLE.
0: POR, 1: Force Enable, 2: Force Disable
**/
UINT8 PchHdaTestPowerClockGating;
-/** Offset 0x093A - Enable HD Audio DMIC_N Link
+/** Offset 0x095A - Enable HD Audio DMIC_N Link
Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
**/
UINT8 PchHdaAudioLinkDmicEnable[2];
-/** Offset 0x093C - DMIC<N> ClkA Pin Muxing (N - DMIC number)
+/** Offset 0x095C - DMIC<N> ClkA Pin Muxing (N - DMIC number)
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
**/
UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
-/** Offset 0x0944 - DMIC<N> ClkB Pin Muxing
+/** Offset 0x0964 - DMIC<N> ClkB Pin Muxing
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_*
**/
UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
-/** Offset 0x094C - Enable HD Audio DSP
+/** Offset 0x096C - Enable HD Audio DSP
Enable/disable HD Audio DSP feature.
$EN_DIS
**/
UINT8 PchHdaDspEnable;
-/** Offset 0x094D - Reserved
+/** Offset 0x096D - Reserved
**/
- UINT8 Reserved34[3];
+ UINT8 Reserved36[3];
-/** Offset 0x0950 - DMIC<N> Data Pin Muxing
+/** Offset 0x0970 - DMIC<N> Data Pin Muxing
Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
**/
UINT32 PchHdaAudioLinkDmicDataPinMux[2];
-/** Offset 0x0958 - Enable HD Audio SSP0 Link
+/** Offset 0x0978 - Enable HD Audio SSP0 Link
Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
**/
UINT8 PchHdaAudioLinkSspEnable[6];
-/** Offset 0x095E - Enable HD Audio SoundWire#N Link
+/** Offset 0x097E - Enable HD Audio SoundWire#N Link
Enable/disable HD Audio SNDW#N link. Muxed with HDA.
**/
UINT8 PchHdaAudioLinkSndwEnable[4];
-/** Offset 0x0962 - iDisp-Link Frequency
+/** Offset 0x0982 - iDisp-Link Frequency
iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
4: 96MHz, 3: 48MHz
**/
UINT8 PchHdaIDispLinkFrequency;
-/** Offset 0x0963 - Reserved
+/** Offset 0x0983 - Reserved
**/
- UINT8 Reserved35;
+ UINT8 Reserved37;
-/** Offset 0x0964 - iDisp-Link T-mode
+/** Offset 0x0984 - iDisp-Link T-mode
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
0: 2T, 2: 4T, 3: 8T, 4: 16T
**/
UINT8 PchHdaIDispLinkTmode;
-/** Offset 0x0965 - iDisplay Audio Codec disconnection
+/** Offset 0x0985 - iDisplay Audio Codec disconnection
0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
$EN_DIS
**/
UINT8 PchHdaIDispCodecDisconnect;
-/** Offset 0x0966 - Reserved
+/** Offset 0x0986 - Reserved
**/
- UINT8 Reserved36[6];
+ UINT8 Reserved38[6];
-/** Offset 0x096C - CNVi DDR RFI Mitigation
+/** Offset 0x098C - CNVi DDR RFI Mitigation
Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviDdrRfim;
-/** Offset 0x096D - Reserved
+/** Offset 0x098D - Reserved
**/
- UINT8 Reserved37[11];
+ UINT8 Reserved39[11];
-/** Offset 0x0978 - Debug Interfaces
+/** Offset 0x0998 - Debug Interfaces
Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
BIT2 - Not used.
**/
UINT8 PcdDebugInterfaceFlags;
-/** Offset 0x0979 - Serial Io Uart Debug Controller Number
+/** Offset 0x0999 - Serial Io Uart Debug Controller Number
Select SerialIo Uart Controller for debug.
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
**/
UINT8 SerialIoUartDebugControllerNumber;
-/** Offset 0x097A - Serial Io Uart Debug Auto Flow
+/** Offset 0x099A - Serial Io Uart Debug Auto Flow
Enables UART hardware flow control, CTS and RTS lines.
$EN_DIS
**/
UINT8 SerialIoUartDebugAutoFlow;
-/** Offset 0x097B - Reserved
+/** Offset 0x099B - Reserved
**/
- UINT8 Reserved38;
+ UINT8 Reserved40;
-/** Offset 0x097C - Serial Io Uart Debug BaudRate
+/** Offset 0x099C - Serial Io Uart Debug BaudRate
Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
**/
UINT32 SerialIoUartDebugBaudRate;
-/** Offset 0x0980 - Serial Io Uart Debug Parity
+/** Offset 0x09A0 - Serial Io Uart Debug Parity
Set default Parity.
0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
**/
UINT8 SerialIoUartDebugParity;
-/** Offset 0x0981 - Serial Io Uart Debug Stop Bits
+/** Offset 0x09A1 - Serial Io Uart Debug Stop Bits
Set default stop bits.
0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
**/
UINT8 SerialIoUartDebugStopBits;
-/** Offset 0x0982 - Serial Io Uart Debug Data Bits
+/** Offset 0x09A2 - Serial Io Uart Debug Data Bits
Set default word length. 0: Default, 5,6,7,8
5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
**/
UINT8 SerialIoUartDebugDataBits;
-/** Offset 0x0983 - Reserved
+/** Offset 0x09A3 - Reserved
**/
- UINT8 Reserved39;
+ UINT8 Reserved41;
-/** Offset 0x0984 - Serial Io Uart Debug Mmio Base
+/** Offset 0x09A4 - Serial Io Uart Debug Mmio Base
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
= SerialIoUartPci.
**/
UINT32 SerialIoUartDebugMmioBase;
-/** Offset 0x0988 - ISA Serial Base selection
+/** Offset 0x09A8 - ISA Serial Base selection
Select ISA Serial Base address. Default is 0x3F8.
0:0x3F8, 1:0x2F8
**/
UINT8 PcdIsaSerialUartBase;
-/** Offset 0x0989 - Reserved
+/** Offset 0x09A9 - Reserved
**/
- UINT8 Reserved40;
+ UINT8 Reserved42;
-/** Offset 0x098A - Ring PLL voltage offset
+/** Offset 0x09AA - Ring PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 RingPllVoltageOffset;
-/** Offset 0x098B - System Agent PLL voltage offset
+/** Offset 0x09AB - System Agent PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 SaPllVoltageOffset;
-/** Offset 0x098C - Memory Controller PLL voltage offset
+/** Offset 0x09AC - Memory Controller PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 McPllVoltageOffset;
-/** Offset 0x098D - TCSS Thunderbolt PCIE Root Port 0 Enable
+/** Offset 0x09AD - TCSS Thunderbolt PCIE Root Port 0 Enable
Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie0En;
-/** Offset 0x098E - TCSS Thunderbolt PCIE Root Port 1 Enable
+/** Offset 0x09AE - TCSS Thunderbolt PCIE Root Port 1 Enable
Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie1En;
-/** Offset 0x098F - TCSS Thunderbolt PCIE Root Port 2 Enable
+/** Offset 0x09AF - TCSS Thunderbolt PCIE Root Port 2 Enable
Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie2En;
-/** Offset 0x0990 - TCSS Thunderbolt PCIE Root Port 3 Enable
+/** Offset 0x09B0 - TCSS Thunderbolt PCIE Root Port 3 Enable
Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie3En;
-/** Offset 0x0991 - TCSS USB HOST (xHCI) Enable
+/** Offset 0x09B1 - TCSS USB HOST (xHCI) Enable
Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
$EN_DIS
**/
UINT8 TcssXhciEn;
-/** Offset 0x0992 - TCSS USB DEVICE (xDCI) Enable
+/** Offset 0x09B2 - TCSS USB DEVICE (xDCI) Enable
Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
$EN_DIS
**/
UINT8 TcssXdciEn;
-/** Offset 0x0993 - TCSS DMA0 Enable
+/** Offset 0x09B3 - TCSS DMA0 Enable
Set TCSS DMA0. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssDma0En;
-/** Offset 0x0994 - TCSS DMA1 Enable
+/** Offset 0x09B4 - TCSS DMA1 Enable
Set TCSS DMA1. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssDma1En;
-/** Offset 0x0995 - PcdSerialDebugBaudRate
+/** Offset 0x09B5 - PcdSerialDebugBaudRate
Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
3:9600, 4:19200, 6:56700, 7:115200
**/
UINT8 PcdSerialDebugBaudRate;
-/** Offset 0x0996 - HobBufferSize
+/** Offset 0x09B6 - HobBufferSize
Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
total HOB size).
0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
**/
UINT8 HobBufferSize;
-/** Offset 0x0997 - Early Command Training
+/** Offset 0x09B7 - Early Command Training
Enables/Disable Early Command Training
$EN_DIS
**/
UINT8 ECT;
-/** Offset 0x0998 - SenseAmp Offset Training
+/** Offset 0x09B8 - SenseAmp Offset Training
Enables/Disable SenseAmp Offset Training
$EN_DIS
**/
UINT8 SOT;
-/** Offset 0x0999 - Early ReadMPR Timing Centering 2D
+/** Offset 0x09B9 - Early ReadMPR Timing Centering 2D
Enables/Disable Early ReadMPR Timing Centering 2D
$EN_DIS
**/
UINT8 ERDMPRTC2D;
-/** Offset 0x099A - Read MPR Training
+/** Offset 0x09BA - Read MPR Training
Enables/Disable Read MPR Training
$EN_DIS
**/
UINT8 RDMPRT;
-/** Offset 0x099B - Receive Enable Training
+/** Offset 0x09BB - Receive Enable Training
Enables/Disable Receive Enable Training
$EN_DIS
**/
UINT8 RCVET;
-/** Offset 0x099C - Jedec Write Leveling
+/** Offset 0x09BC - Jedec Write Leveling
Enables/Disable Jedec Write Leveling
$EN_DIS
**/
UINT8 JWRL;
-/** Offset 0x099D - Early Write Time Centering 2D
+/** Offset 0x09BD - Early Write Time Centering 2D
Enables/Disable Early Write Time Centering 2D
$EN_DIS
**/
UINT8 EWRTC2D;
-/** Offset 0x099E - Early Read Time Centering 2D
+/** Offset 0x09BE - Early Read Time Centering 2D
Enables/Disable Early Read Time Centering 2D
$EN_DIS
**/
UINT8 ERDTC2D;
-/** Offset 0x099F - Reserved
+/** Offset 0x09BF - Reserved
**/
- UINT8 Reserved41;
+ UINT8 Reserved43;
-/** Offset 0x09A0 - Write Timing Centering 1D
+/** Offset 0x09C0 - Write Timing Centering 1D
Enables/Disable Write Timing Centering 1D
$EN_DIS
**/
UINT8 WRTC1D;
-/** Offset 0x09A1 - Write Voltage Centering 1D
+/** Offset 0x09C1 - Write Voltage Centering 1D
Enables/Disable Write Voltage Centering 1D
$EN_DIS
**/
UINT8 WRVC1D;
-/** Offset 0x09A2 - Read Timing Centering 1D
+/** Offset 0x09C2 - Read Timing Centering 1D
Enables/Disable Read Timing Centering 1D
$EN_DIS
**/
UINT8 RDTC1D;
-/** Offset 0x09A3 - Read Voltage Centering 1D
+/** Offset 0x09C3 - Read Voltage Centering 1D
Enable/Disable Read Voltage Centering 1D
$EN_DIS
**/
UINT8 RDVC1D;
-/** Offset 0x09A4 - Reserved
+/** Offset 0x09C4 - Reserved
**/
- UINT8 Reserved42[2];
+ UINT8 Reserved44[2];
-/** Offset 0x09A6 - Read ODT Training
+/** Offset 0x09C6 - Read ODT Training
Enables/Disable Read ODT Training
$EN_DIS
**/
UINT8 RDODTT;
-/** Offset 0x09A7 - Read Equalization Training
+/** Offset 0x09C7 - Read Equalization Training
Enables/Disable Read Equalization Training
$EN_DIS
**/
UINT8 RDEQT;
-/** Offset 0x09A8 - Reserved
+/** Offset 0x09C8 - Reserved
**/
- UINT8 Reserved43;
+ UINT8 Reserved45;
-/** Offset 0x09A9 - Write Timing Centering 2D
+/** Offset 0x09C9 - Write Timing Centering 2D
Enables/Disable Write Timing Centering 2D
$EN_DIS
**/
UINT8 WRTC2D;
-/** Offset 0x09AA - Read Timing Centering 2D
+/** Offset 0x09CA - Read Timing Centering 2D
Enables/Disable Read Timing Centering 2D
$EN_DIS
**/
UINT8 RDTC2D;
-/** Offset 0x09AB - Write Voltage Centering 2D
+/** Offset 0x09CB - Write Voltage Centering 2D
Enables/Disable Write Voltage Centering 2D
$EN_DIS
**/
UINT8 WRVC2D;
-/** Offset 0x09AC - Read Voltage Centering 2D
+/** Offset 0x09CC - Read Voltage Centering 2D
Enables/Disable Read Voltage Centering 2D
$EN_DIS
**/
UINT8 RDVC2D;
-/** Offset 0x09AD - Command Voltage Centering
+/** Offset 0x09CD - Command Voltage Centering
Enables/Disable Command Voltage Centering
$EN_DIS
**/
UINT8 CMDVC;
-/** Offset 0x09AE - Late Command Training
+/** Offset 0x09CE - Late Command Training
Enables/Disable Late Command Training
$EN_DIS
**/
UINT8 LCT;
-/** Offset 0x09AF - Turn Around Timing Training
+/** Offset 0x09CF - Turn Around Timing Training
Enables/Disable Turn Around Timing Training
$EN_DIS
**/
UINT8 TAT;
-/** Offset 0x09B0 - Rank Margin Tool
+/** Offset 0x09D0 - Rank Margin Tool
Enable/disable Rank Margin Tool
$EN_DIS
**/
UINT8 RMT;
-/** Offset 0x09B1 - Reserved
+/** Offset 0x09D1 - Reserved
**/
- UINT8 Reserved44;
+ UINT8 Reserved46;
-/** Offset 0x09B2 - DIMM SPD Alias Test
+/** Offset 0x09D2 - DIMM SPD Alias Test
Enables/Disable DIMM SPD Alias Test
$EN_DIS
**/
UINT8 ALIASCHK;
-/** Offset 0x09B3 - Reserved
-**/
- UINT8 Reserved45;
-
-/** Offset 0x09B4 - Retrain Margin Check
+/** Offset 0x09D3 - Retrain Margin Check
Enables/Disable Retrain Margin Check
$EN_DIS
**/
UINT8 RMC;
-/** Offset 0x09B5 - Reserved
+/** Offset 0x09D4 - Reserved
**/
- UINT8 Reserved46;
+ UINT8 Reserved47;
-/** Offset 0x09B6 - Dimm ODT Training
+/** Offset 0x09D5 - Dimm ODT Training
Enables/Disable Dimm ODT Training
$EN_DIS
**/
UINT8 DIMMODTT;
-/** Offset 0x09B7 - DIMM RON Training
+/** Offset 0x09D6 - DIMM RON Training
Enables/Disable DIMM RON Training
$EN_DIS
**/
UINT8 DIMMRONT;
-/** Offset 0x09B8 - TxDqTCO Comp Training
+/** Offset 0x09D7 - TxDqTCO Comp Training
Enable/Disable TxDqTCO Comp Training
$EN_DIS
**/
UINT8 TXTCO;
-/** Offset 0x09B9 - ClkTCO Comp Training
+/** Offset 0x09D8 - ClkTCO Comp Training
Enable/Disable ClkTCO Comp Training
$EN_DIS
**/
UINT8 CLKTCO;
-/** Offset 0x09BA - CMD Slew Rate Training
+/** Offset 0x09D9 - CMD Slew Rate Training
Enable/Disable CMD Slew Rate Training
$EN_DIS
**/
UINT8 CMDSR;
-/** Offset 0x09BB - Reserved
+/** Offset 0x09DA - Reserved
**/
- UINT8 Reserved47[2];
+ UINT8 Reserved48[2];
-/** Offset 0x09BD - DIMM CA ODT Training
+/** Offset 0x09DC - DIMM CA ODT Training
Enable/Disable DIMM CA ODT Training
$EN_DIS
**/
UINT8 DIMMODTCA;
-/** Offset 0x09BE - Reserved
+/** Offset 0x09DD - Reserved
**/
- UINT8 Reserved48[3];
+ UINT8 Reserved49[3];
-/** Offset 0x09C1 - Read Vref Decap Training
+/** Offset 0x09E0 - Read Vref Decap Training
Enable/Disable Read Vref Decap Training
$EN_DIS
**/
UINT8 RDVREFDC;
-/** Offset 0x09C2 - Vddq Training
+/** Offset 0x09E1 - Vddq Training
Enable/Disable Vddq Training
$EN_DIS
**/
UINT8 VDDQT;
-/** Offset 0x09C3 - Rank Margin Tool Per Bit
+/** Offset 0x09E2 - Rank Margin Tool Per Bit
Enable/Disable Rank Margin Tool Per Bit
$EN_DIS
**/
UINT8 RMTBIT;
-/** Offset 0x09C4 - Reserved
+/** Offset 0x09E3 - Reserved
**/
- UINT8 Reserved49[4];
+ UINT8 Reserved50[4];
-/** Offset 0x09C8 - Duty Cycle Correction Training
+/** Offset 0x09E7 - Duty Cycle Correction Training
Enable/Disable Duty Cycle Correction Training
$EN_DIS
**/
UINT8 DCC;
-/** Offset 0x09C9 - Reserved
+/** Offset 0x09E8 - Reserved
**/
- UINT8 Reserved50[17];
+ UINT8 Reserved51[17];
-/** Offset 0x09DA - ECC Support
+/** Offset 0x09F9 - ECC Support
Enables/Disable ECC Support
$EN_DIS
**/
UINT8 EccSupport;
-/** Offset 0x09DB - Ibecc
+/** Offset 0x09FA - Ibecc
In-Band ECC Support
$EN_DIS
**/
UINT8 Ibecc;
-/** Offset 0x09DC - IbeccParity
+/** Offset 0x09FB - IbeccParity
In-Band ECC Parity Control
$EN_DIS
**/
UINT8 IbeccParity;
-/** Offset 0x09DD - IbeccOperationMode
+/** Offset 0x09FC - IbeccOperationMode
In-Band ECC Operation Mode
0:Protect base on address range, 1: Non-protected, 2: All protected
**/
UINT8 IbeccOperationMode;
-/** Offset 0x09DE - IbeccProtectedRegionEnable
+/** Offset 0x09FD - IbeccProtectedRegionEnable
In-Band ECC Protected Region Enable
$EN_DIS
**/
UINT8 IbeccProtectedRegionEnable[8];
-/** Offset 0x09E6 - IbeccProtectedRegionBases
+/** Offset 0x0A05 - Reserved
+**/
+ UINT8 Reserved52;
+
+/** Offset 0x0A06 - IbeccProtectedRegionBases
IBECC Protected Region Bases per IBECC instance
**/
UINT16 IbeccProtectedRegionBase[8];
-/** Offset 0x09F6 - IbeccProtectedRegionMasks
+/** Offset 0x0A16 - IbeccProtectedRegionMasks
IBECC Protected Region Masks
**/
UINT16 IbeccProtectedRegionMask[8];
-/** Offset 0x0A06 - IbeccProtectedRegionOverallBases
+/** Offset 0x0A26 - IbeccProtectedRegionOverallBases
IBECC Protected Region Bases based on enabled IBECC instance
**/
UINT16 IbeccProtectedRegionOverallBase[8];
-/** Offset 0x0A16 - Memory Remap
+/** Offset 0x0A36 - Memory Remap
Enables/Disable Memory Remap
$EN_DIS
**/
UINT8 RemapEnable;
-/** Offset 0x0A17 - Rank Interleave support
+/** Offset 0x0A37 - Rank Interleave support
Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
the same time.
$EN_DIS
**/
UINT8 RankInterleave;
-/** Offset 0x0A18 - Enhanced Interleave support
+/** Offset 0x0A38 - Enhanced Interleave support
Enables/Disable Enhanced Interleave support
$EN_DIS
**/
UINT8 EnhancedInterleave;
-/** Offset 0x0A19 - Ch Hash Support
+/** Offset 0x0A39 - Ch Hash Support
Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
$EN_DIS
**/
UINT8 ChHashEnable;
-/** Offset 0x0A1A - Extern Therm Status
+/** Offset 0x0A3A - Extern Therm Status
Enables/Disable Extern Therm Status
$EN_DIS
**/
UINT8 EnableExtts;
-/** Offset 0x0A1B - DDR PowerDown and idle counter
+/** Offset 0x0A3B - DDR PowerDown and idle counter
Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
$EN_DIS
**/
UINT8 EnablePwrDn;
-/** Offset 0x0A1C - DDR PowerDown and idle counter
+/** Offset 0x0A3C - DDR PowerDown and idle counter
Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
$EN_DIS
**/
UINT8 EnablePwrDnLpddr;
-/** Offset 0x0A1D - SelfRefresh Enable
+/** Offset 0x0A3D - SelfRefresh Enable
Enables/Disable SelfRefresh Enable
$EN_DIS
**/
UINT8 SrefCfgEna;
-/** Offset 0x0A1E - Throttler CKEMin Defeature
+/** Offset 0x0A3E - Throttler CKEMin Defeature
Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
$EN_DIS
**/
UINT8 ThrtCkeMinDefeatLpddr;
-/** Offset 0x0A1F - Throttler CKEMin Defeature
+/** Offset 0x0A3F - Throttler CKEMin Defeature
Enables/Disable Throttler CKEMin Defeature
$EN_DIS
**/
UINT8 ThrtCkeMinDefeat;
-/** Offset 0x0A20 - Reserved
+/** Offset 0x0A40 - Reserved
**/
- UINT8 Reserved51;
+ UINT8 Reserved53;
-/** Offset 0x0A21 - Exit On Failure (MRC)
+/** Offset 0x0A41 - Exit On Failure (MRC)
Enables/Disable Exit On Failure (MRC)
$EN_DIS
**/
UINT8 ExitOnFailure;
-/** Offset 0x0A22 - Reserved
+/** Offset 0x0A42 - Reserved
**/
- UINT8 Reserved52[4];
+ UINT8 Reserved54[4];
-/** Offset 0x0A26 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+/** Offset 0x0A46 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
$EN_DIS
**/
UINT8 Ddr4DdpSharedZq;
-/** Offset 0x0A27 - Ch Hash Interleaved Bit
+/** Offset 0x0A47 - Ch Hash Interleaved Bit
Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
**/
UINT8 ChHashInterleaveBit;
-/** Offset 0x0A28 - Ch Hash Mask
+/** Offset 0x0A48 - Ch Hash Mask
Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
BITS [19:6] Default is 0x30CC
**/
UINT16 ChHashMask;
-/** Offset 0x0A2A - Reserved
+/** Offset 0x0A4A - Reserved
**/
- UINT8 Reserved53[2];
+ UINT8 Reserved55[2];
-/** Offset 0x0A2C - Base reference clock value
+/** Offset 0x0A4C - Base reference clock value
Base reference clock value, in Hertz(Default is 125Hz)
100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
**/
UINT32 BClkFrequency;
-/** Offset 0x0A30 - EPG DIMM Idd3N
+/** Offset 0x0A50 - EPG DIMM Idd3N
Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
a per DIMM basis. Default is 26
**/
UINT16 Idd3n;
-/** Offset 0x0A32 - EPG DIMM Idd3P
+/** Offset 0x0A52 - EPG DIMM Idd3P
Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
on a per DIMM basis. Default is 11
**/
UINT16 Idd3p;
-/** Offset 0x0A34 - CMD Normalization
+/** Offset 0x0A54 - CMD Normalization
Enable/Disable CMD Normalization
$EN_DIS
**/
UINT8 CMDNORM;
-/** Offset 0x0A35 - Early DQ Write Drive Strength and Equalization Training
+/** Offset 0x0A55 - Early DQ Write Drive Strength and Equalization Training
Enable/Disable Early DQ Write Drive Strength and Equalization Training
$EN_DIS
**/
UINT8 EWRDSEQ;
-/** Offset 0x0A36 - Idle Energy Mc0Ch0Dimm0
+/** Offset 0x0A56 - Idle Energy Mc0Ch0Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch0Dimm0;
-/** Offset 0x0A37 - Idle Energy Mc0Ch0Dimm1
+/** Offset 0x0A57 - Idle Energy Mc0Ch0Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch0Dimm1;
-/** Offset 0x0A38 - Idle Energy Mc0Ch1Dimm0
+/** Offset 0x0A58 - Idle Energy Mc0Ch1Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch1Dimm0;
-/** Offset 0x0A39 - Idle Energy Mc0Ch1Dimm1
+/** Offset 0x0A59 - Idle Energy Mc0Ch1Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch1Dimm1;
-/** Offset 0x0A3A - Idle Energy Mc1Ch0Dimm0
+/** Offset 0x0A5A - Idle Energy Mc1Ch0Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch0Dimm0;
-/** Offset 0x0A3B - Idle Energy Mc1Ch0Dimm1
+/** Offset 0x0A5B - Idle Energy Mc1Ch0Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch0Dimm1;
-/** Offset 0x0A3C - Idle Energy Mc1Ch1Dimm0
+/** Offset 0x0A5C - Idle Energy Mc1Ch1Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch1Dimm0;
-/** Offset 0x0A3D - Idle Energy Mc1Ch1Dimm1
+/** Offset 0x0A5D - Idle Energy Mc1Ch1Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch1Dimm1;
-/** Offset 0x0A3E - PowerDown Energy Mc0Ch0Dimm0
+/** Offset 0x0A5E - PowerDown Energy Mc0Ch0Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch0Dimm0;
-/** Offset 0x0A3F - PowerDown Energy Mc0Ch0Dimm1
+/** Offset 0x0A5F - PowerDown Energy Mc0Ch0Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch0Dimm1;
-/** Offset 0x0A40 - PowerDown Energy Mc0Ch1Dimm0
+/** Offset 0x0A60 - PowerDown Energy Mc0Ch1Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch1Dimm0;
-/** Offset 0x0A41 - PowerDown Energy Mc0Ch1Dimm1
+/** Offset 0x0A61 - PowerDown Energy Mc0Ch1Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch1Dimm1;
-/** Offset 0x0A42 - PowerDown Energy Mc1Ch0Dimm0
+/** Offset 0x0A62 - PowerDown Energy Mc1Ch0Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch0Dimm0;
-/** Offset 0x0A43 - PowerDown Energy Mc1Ch0Dimm1
+/** Offset 0x0A63 - PowerDown Energy Mc1Ch0Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch0Dimm1;
-/** Offset 0x0A44 - PowerDown Energy Mc1Ch1Dimm0
+/** Offset 0x0A64 - PowerDown Energy Mc1Ch1Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch1Dimm0;
-/** Offset 0x0A45 - PowerDown Energy Mc1Ch1Dimm1
+/** Offset 0x0A65 - PowerDown Energy Mc1Ch1Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch1Dimm1;
-/** Offset 0x0A46 - Activate Energy Mc0Ch0Dimm0
+/** Offset 0x0A66 - Activate Energy Mc0Ch0Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch0Dimm0;
-/** Offset 0x0A47 - Activate Energy Mc0Ch0Dimm1
+/** Offset 0x0A67 - Activate Energy Mc0Ch0Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch0Dimm1;
-/** Offset 0x0A48 - Activate Energy Mc0Ch1Dimm0
+/** Offset 0x0A68 - Activate Energy Mc0Ch1Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch1Dimm0;
-/** Offset 0x0A49 - Activate Energy Mc0Ch1Dimm1
+/** Offset 0x0A69 - Activate Energy Mc0Ch1Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch1Dimm1;
-/** Offset 0x0A4A - Activate Energy Mc1Ch0Dimm0
+/** Offset 0x0A6A - Activate Energy Mc1Ch0Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch0Dimm0;
-/** Offset 0x0A4B - Activate Energy Mc1Ch0Dimm1
+/** Offset 0x0A6B - Activate Energy Mc1Ch0Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch0Dimm1;
-/** Offset 0x0A4C - Activate Energy Mc1Ch1Dimm0
+/** Offset 0x0A6C - Activate Energy Mc1Ch1Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch1Dimm0;
-/** Offset 0x0A4D - Activate Energy Mc1Ch1Dimm1
+/** Offset 0x0A6D - Activate Energy Mc1Ch1Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch1Dimm1;
-/** Offset 0x0A4E - Read Energy Mc0Ch0Dimm0
+/** Offset 0x0A6E - Read Energy Mc0Ch0Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch0Dimm0;
-/** Offset 0x0A4F - Read Energy Mc0Ch0Dimm1
+/** Offset 0x0A6F - Read Energy Mc0Ch0Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch0Dimm1;
-/** Offset 0x0A50 - Read Energy Mc0Ch1Dimm0
+/** Offset 0x0A70 - Read Energy Mc0Ch1Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch1Dimm0;
-/** Offset 0x0A51 - Read Energy Mc0Ch1Dimm1
+/** Offset 0x0A71 - Read Energy Mc0Ch1Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch1Dimm1;
-/** Offset 0x0A52 - Read Energy Mc1Ch0Dimm0
+/** Offset 0x0A72 - Read Energy Mc1Ch0Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch0Dimm0;
-/** Offset 0x0A53 - Read Energy Mc1Ch0Dimm1
+/** Offset 0x0A73 - Read Energy Mc1Ch0Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch0Dimm1;
-/** Offset 0x0A54 - Read Energy Mc1Ch1Dimm0
+/** Offset 0x0A74 - Read Energy Mc1Ch1Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch1Dimm0;
-/** Offset 0x0A55 - Read Energy Mc1Ch1Dimm1
+/** Offset 0x0A75 - Read Energy Mc1Ch1Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch1Dimm1;
-/** Offset 0x0A56 - Write Energy Mc0Ch0Dimm0
+/** Offset 0x0A76 - Write Energy Mc0Ch0Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch0Dimm0;
-/** Offset 0x0A57 - Write Energy Mc0Ch0Dimm1
+/** Offset 0x0A77 - Write Energy Mc0Ch0Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch0Dimm1;
-/** Offset 0x0A58 - Write Energy Mc0Ch1Dimm0
+/** Offset 0x0A78 - Write Energy Mc0Ch1Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch1Dimm0;
-/** Offset 0x0A59 - Write Energy Mc0Ch1Dimm1
+/** Offset 0x0A79 - Write Energy Mc0Ch1Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch1Dimm1;
-/** Offset 0x0A5A - Write Energy Mc1Ch0Dimm0
+/** Offset 0x0A7A - Write Energy Mc1Ch0Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch0Dimm0;
-/** Offset 0x0A5B - Write Energy Mc1Ch0Dimm1
+/** Offset 0x0A7B - Write Energy Mc1Ch0Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch0Dimm1;
-/** Offset 0x0A5C - Write Energy Mc1Ch1Dimm0
+/** Offset 0x0A7C - Write Energy Mc1Ch1Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch1Dimm0;
-/** Offset 0x0A5D - Write Energy Mc1Ch1Dimm1
+/** Offset 0x0A7D - Write Energy Mc1Ch1Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch1Dimm1;
-/** Offset 0x0A5E - Throttler CKEMin Timer
+/** Offset 0x0A7E - Throttler CKEMin Timer
Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
Dfault is 0x00
**/
UINT8 ThrtCkeMinTmr;
-/** Offset 0x0A5F - Reserved
+/** Offset 0x0A7F - Reserved
**/
- UINT8 Reserved54[2];
+ UINT8 Reserved56[2];
-/** Offset 0x0A61 - Rapl Power Floor Ch0
+/** Offset 0x0A81 - Rapl Power Floor Ch0
Power budget ,range[255;0],(0= 5.3W Def)
**/
UINT8 RaplPwrFlCh0;
-/** Offset 0x0A62 - Rapl Power Floor Ch1
+/** Offset 0x0A82 - Rapl Power Floor Ch1
Power budget ,range[255;0],(0= 5.3W Def)
**/
UINT8 RaplPwrFlCh1;
-/** Offset 0x0A63 - Command Rate Support
+/** Offset 0x0A83 - Command Rate Support
CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS
**/
UINT8 EnCmdRate;
-/** Offset 0x0A64 - Reserved
+/** Offset 0x0A84 - Reserved
**/
- UINT8 Reserved55;
+ UINT8 Reserved57;
-/** Offset 0x0A65 - Energy Performance Gain
+/** Offset 0x0A85 - Energy Performance Gain
Enable/disable Energy Performance Gain. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 EpgEnable;
-/** Offset 0x0A66 - Reserved
+/** Offset 0x0A86 - Reserved
**/
- UINT8 Reserved56;
+ UINT8 Reserved58;
-/** Offset 0x0A67 - User Manual Threshold
+/** Offset 0x0A87 - User Manual Threshold
Disabled: Predefined threshold will be used.\n
Enabled: User Input will be used.
$EN_DIS
**/
UINT8 UserThresholdEnable;
-/** Offset 0x0A68 - User Manual Budget
+/** Offset 0x0A88 - User Manual Budget
Disabled: Configuration of memories will defined the Budget value.\n
Enabled: User Input will be used.
$EN_DIS
**/
UINT8 UserBudgetEnable;
-/** Offset 0x0A69 - Power Down Mode
+/** Offset 0x0A89 - Power Down Mode
This option controls command bus tristating during idle periods
0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto
**/
UINT8 PowerDownMode;
-/** Offset 0x0A6A - Pwr Down Idle Timer
+/** Offset 0x0A8A - Pwr Down Idle Timer
The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
AUTO: 64 for ULX/ULT, 128 for DT/Halo
**/
UINT8 PwdwnIdleCounter;
-/** Offset 0x0A6B - Page Close Idle Timeout
+/** Offset 0x0A8B - Page Close Idle Timeout
This option controls Page Close Idle Timeout
0:Enabled, 1:Disabled
**/
UINT8 DisPgCloseIdleTimeout;
-/** Offset 0x0A6C - Bitmask of ranks that have CA bus terminated
+/** Offset 0x0A8C - Bitmask of ranks that have CA bus terminated
Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default,
Rank0 is terminating and Rank1 is non-terminating</b>
**/
UINT8 CmdRanksTerminated;
-/** Offset 0x0A6D - PcdSerialDebugLevel
+/** Offset 0x0A8D - PcdSerialDebugLevel
Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose.
@@ -2659,72 +2661,72 @@ typedef struct {
**/
UINT8 PcdSerialDebugLevel;
-/** Offset 0x0A6E - Reserved
+/** Offset 0x0A8E - Reserved
**/
- UINT8 Reserved57[7];
+ UINT8 Reserved59[7];
-/** Offset 0x0A75 - Ask MRC to clear memory content
+/** Offset 0x0A95 - Ask MRC to clear memory content
Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
$EN_DIS
**/
UINT8 CleanMemory;
-/** Offset 0x0A76 - TCSS USB Port Enable
+/** Offset 0x0A96 - TCSS USB Port Enable
Bitmap for per port enabling
**/
UINT8 UsbTcPortEnPreMem;
-/** Offset 0x0A77 - Reserved
+/** Offset 0x0A97 - Reserved
**/
- UINT8 Reserved58;
+ UINT8 Reserved60;
-/** Offset 0x0A78 - Post Code Output Port
+/** Offset 0x0A98 - Post Code Output Port
This option configures Post Code Output Port
**/
UINT16 PostCodeOutputPort;
-/** Offset 0x0A7A - RMTLoopCount
+/** Offset 0x0A9A - RMTLoopCount
Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
**/
UINT8 RMTLoopCount;
-/** Offset 0x0A7B - Enable/Disable SA CRID
+/** Offset 0x0A9B - Enable/Disable SA CRID
Enable: SA CRID, Disable (Default): SA CRID
$EN_DIS
**/
UINT8 CridEnable;
-/** Offset 0x0A7C - BCLK RFI Frequency
+/** Offset 0x0A9C - BCLK RFI Frequency
Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
RFI Tuning</b>. Range is 98Mhz-100Mhz.
**/
UINT32 BclkRfiFreq[4];
-/** Offset 0x0A8C - Size of PCIe IMR.
+/** Offset 0x0AAC - Size of PCIe IMR.
Size of PCIe IMR in megabytes
**/
UINT16 PcieImrSize;
-/** Offset 0x0A8E - Enable PCIe IMR
+/** Offset 0x0AAE - Enable PCIe IMR
0: Disable(AUTO), 1: Enable
$EN_DIS
**/
UINT8 PcieImrEnabled;
-/** Offset 0x0A8F - Enable PCIe IMR
+/** Offset 0x0AAF - Enable PCIe IMR
1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select
the Root port location from PCH PCIe or SA PCIe
$EN_DIS
**/
UINT8 PcieImrRpLocation;
-/** Offset 0x0A90 - Root port number for IMR.
+/** Offset 0x0AB0 - Root port number for IMR.
Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port
from 0 to 23 and if it is SA PCIe then select root port from 0 to 3
**/
UINT8 PcieImrRpSelection;
-/** Offset 0x0A91 - SerialDebugMrcLevel
+/** Offset 0x0AB1 - SerialDebugMrcLevel
MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose.
@@ -2733,204 +2735,208 @@ typedef struct {
**/
UINT8 SerialDebugMrcLevel;
-/** Offset 0x0A92 - Reserved
+/** Offset 0x0AB2 - Reserved
**/
- UINT8 Reserved59[11];
+ UINT8 Reserved61[13];
-/** Offset 0x0A9D - Command Pins Mapping
+/** Offset 0x0ABF - Command Pins Mapping
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
**/
UINT8 Lp5CccConfig;
-/** Offset 0x0A9E - Command Pins Mirrored
+/** Offset 0x0AC0 - Command Pins Mirrored
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
**/
UINT8 CmdMirror;
-/** Offset 0x0A9F - Reserved
+/** Offset 0x0AC1 - Reserved
**/
- UINT8 Reserved60[4];
+ UINT8 Reserved62[4];
-/** Offset 0x0AA3 - Skip external display device scanning
+/** Offset 0x0AC5 - Skip external display device scanning
Enable: Do not scan for external display device, Disable (Default): Scan external
display devices
$EN_DIS
**/
UINT8 SkipExtGfxScan;
-/** Offset 0x0AA4 - Generate BIOS Data ACPI Table
+/** Offset 0x0AC6 - Generate BIOS Data ACPI Table
Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
$EN_DIS
**/
UINT8 BdatEnable;
-/** Offset 0x0AA5 - Lock PCU Thermal Management registers
+/** Offset 0x0AC7 - Lock PCU Thermal Management registers
Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
$EN_DIS
**/
UINT8 LockPTMregs;
-/** Offset 0x0AA6 - Panel Power Enable
+/** Offset 0x0AC8 - Panel Power Enable
Control for enabling/disabling VDD force bit (Required only for early enabling of
eDP panel). 0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 PanelPowerEnable;
-/** Offset 0x0AA7 - BdatTestType
+/** Offset 0x0AC9 - BdatTestType
Indicates the type of Memory Training data to populate into the BDAT ACPI table.
0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
**/
UINT8 BdatTestType;
-/** Offset 0x0AA8 - PMR Size
+/** Offset 0x0ACA - Reserved
+**/
+ UINT8 Reserved63[2];
+
+/** Offset 0x0ACC - PMR Size
Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
**/
UINT32 DmaBufferSize;
-/** Offset 0x0AAC - The policy for VTd driver behavior
+/** Offset 0x0AD0 - The policy for VTd driver behavior
BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS
**/
UINT8 PreBootDmaMask;
-/** Offset 0x0AAD - Reserved
+/** Offset 0x0AD1 - Reserved
**/
- UINT8 Reserved61[95];
+ UINT8 Reserved64[95];
-/** Offset 0x0B0C - TotalFlashSize
+/** Offset 0x0B30 - TotalFlashSize
Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
**/
UINT16 TotalFlashSize;
-/** Offset 0x0B0E - BiosSize
+/** Offset 0x0B32 - BiosSize
The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected
Range) so that a BIOS Update Script can be stored in the DPR.
**/
UINT16 BiosSize;
-/** Offset 0x0B10 - Reserved
+/** Offset 0x0B34 - Reserved
**/
- UINT8 Reserved62[12];
+ UINT8 Reserved65[12];
-/** Offset 0x0B1C - Smbus dynamic power gating
+/** Offset 0x0B40 - Smbus dynamic power gating
Disable or Enable Smbus dynamic power gating.
$EN_DIS
**/
UINT8 SmbusDynamicPowerGating;
-/** Offset 0x0B1D - Disable and Lock Watch Dog Register
+/** Offset 0x0B41 - Disable and Lock Watch Dog Register
Set 1 to clear WDT status, then disable and lock WDT registers.
$EN_DIS
**/
UINT8 WdtDisableAndLock;
-/** Offset 0x0B1E - SMBUS SPD Write Disable
+/** Offset 0x0B42 - SMBUS SPD Write Disable
Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
Disable bit. For security recommendations, SPD write disable bit must be set.
$EN_DIS
**/
UINT8 SmbusSpdWriteDisable;
-/** Offset 0x0B1F - HECI Timeouts
+/** Offset 0x0B43 - HECI Timeouts
0: Disable, 1: Enable (Default) timeout check for HECI
$EN_DIS
**/
UINT8 HeciTimeouts;
-/** Offset 0x0B20 - Force ME DID Init Status
+/** Offset 0x0B44 - Force ME DID Init Status
Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
ME DID init stat value
$EN_DIS
**/
UINT8 DidInitStat;
-/** Offset 0x0B21 - CPU Replaced Polling Disable
+/** Offset 0x0B45 - CPU Replaced Polling Disable
Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
$EN_DIS
**/
UINT8 DisableCpuReplacedPolling;
-/** Offset 0x0B22 - Check HECI message before send
+/** Offset 0x0B46 - Check HECI message before send
Test, 0: disable, 1: enable, Enable/Disable message check.
$EN_DIS
**/
UINT8 DisableMessageCheck;
-/** Offset 0x0B23 - Skip MBP HOB
+/** Offset 0x0B47 - Skip MBP HOB
Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
$EN_DIS
**/
UINT8 SkipMbpHob;
-/** Offset 0x0B24 - HECI2 Interface Communication
+/** Offset 0x0B48 - HECI2 Interface Communication
Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
$EN_DIS
**/
UINT8 HeciCommunication2;
-/** Offset 0x0B25 - Enable KT device
+/** Offset 0x0B49 - Enable KT device
Test, 0: disable, 1: enable, Enable or Disable KT device.
$EN_DIS
**/
UINT8 KtDeviceEnable;
-/** Offset 0x0B26 - Skip CPU replacement check
+/** Offset 0x0B4A - Skip CPU replacement check
Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
$EN_DIS
**/
UINT8 SkipCpuReplacementCheck;
-/** Offset 0x0B27 - Avx2 Voltage Guardband Scaling Factor
+/** Offset 0x0B4B - Avx2 Voltage Guardband Scaling Factor
AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
1/100 units, where a value of 125 would apply a 1.25 scale factor.
**/
UINT8 Avx2VoltageScaleFactor;
-/** Offset 0x0B28 - Avx512 Voltage Guardband Scaling Factor
+/** Offset 0x0B4C - Avx512 Voltage Guardband Scaling Factor
AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200
in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
**/
UINT8 Avx512VoltageScaleFactor;
-/** Offset 0x0B29 - Serial Io Uart Debug Mode
+/** Offset 0x0B4D - Serial Io Uart Debug Mode
Select SerialIo Uart Controller mode
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
4:SerialIoUartSkipInit
**/
UINT8 SerialIoUartDebugMode;
-/** Offset 0x0B2A - Reserved
+/** Offset 0x0B4E - Reserved
**/
- UINT8 Reserved63[2];
+ UINT8 Reserved66[2];
-/** Offset 0x0B2C - SerialIoUartDebugRxPinMux - FSPM
+/** Offset 0x0B50 - SerialIoUartDebugRxPinMux - FSPM
Select RX pin muxing for SerialIo UART used for debug
**/
UINT32 SerialIoUartDebugRxPinMux;
-/** Offset 0x0B30 - SerialIoUartDebugTxPinMux - FSPM
+/** Offset 0x0B54 - SerialIoUartDebugTxPinMux - FSPM
Select TX pin muxing for SerialIo UART used for debug
**/
UINT32 SerialIoUartDebugTxPinMux;
-/** Offset 0x0B34 - SerialIoUartDebugRtsPinMux - FSPM
+/** Offset 0x0B58 - SerialIoUartDebugRtsPinMux - FSPM
Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
for possible values.
**/
UINT32 SerialIoUartDebugRtsPinMux;
-/** Offset 0x0B38 - SerialIoUartDebugCtsPinMux - FSPM
+/** Offset 0x0B5C - SerialIoUartDebugCtsPinMux - FSPM
Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
for possible values.
**/
UINT32 SerialIoUartDebugCtsPinMux;
-/** Offset 0x0B3C - Reserved
+/** Offset 0x0B60 - Reserved
**/
- UINT8 Reserved64[20];
+ UINT8 Reserved67[24];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
@@ -2949,11 +2955,11 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
-/** Offset 0x0B50
+/** Offset 0x0B78
**/
- UINT8 UnusedUpdSpace34[6];
+ UINT8 UnusedUpdSpace38[6];
-/** Offset 0x0B56
+/** Offset 0x0B7E
**/
UINT16 UpdTerminator;
} FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h
index 65ac66e039d..c39cb12bb87 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h
@@ -407,9 +407,15 @@ typedef struct {
**/
UINT8 PchSerialIoI2cPadsTermination[8];
-/** Offset 0x02A8 - Reserved
+/** Offset 0x02A8 - I3C Device Mode
+ Selects I3c operation mode. Available modes: 0:SerialIoI3cDisabled, 1:SerialIoI3cPci,
+ 2:SerialIoI3cPhantom (only applicable to I3C1, controlls GPIO enabling)
**/
- UINT8 Reserved8[40];
+ UINT8 SerialIoI3cMode[2];
+
+/** Offset 0x02AA - Reserved
+**/
+ UINT8 Reserved8[38];
/** Offset 0x02D0 - ISH GP GPIO Pin Muxing
Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER
@@ -685,639 +691,636 @@ typedef struct {
**/
UINT8 PcieDpc[28];
-/** Offset 0x04AC - PCIe DPC extensions enable/disable
- Enable/disable Downstream Port Containment Extensions for PCIE Root Ports.
-**/
- UINT8 PcieEdpc[28];
-
-/** Offset 0x04C8 - USB PDO Programming
+/** Offset 0x04AC - USB PDO Programming
Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
during later phase. 1: enable, 0: disable
$EN_DIS
**/
UINT8 UsbPdoProgramming;
-/** Offset 0x04C9 - Reserved
+/** Offset 0x04AD - Reserved
**/
UINT8 Reserved13[3];
-/** Offset 0x04CC - Power button debounce configuration
+/** Offset 0x04B0 - Power button debounce configuration
Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
**/
UINT32 PmcPowerButtonDebounce;
-/** Offset 0x04D0 - Reserved
+/** Offset 0x04B4 - Reserved
**/
UINT8 Reserved14;
-/** Offset 0x04D1 - PCH eSPI Link Configuration Lock (SBLCL)
+/** Offset 0x04B5 - PCH eSPI Link Configuration Lock (SBLCL)
Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target
addresseses from range 0x0 - 0x7FF
$EN_DIS
**/
UINT8 PchEspiLockLinkConfiguration;
-/** Offset 0x04D2 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
+/** Offset 0x04B6 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
**/
UINT8 PchFivrExtV1p05RailEnabledStates;
-/** Offset 0x04D3 - Mask to enable the platform configuration of external V1p05 VR rail
+/** Offset 0x04B7 - Mask to enable the platform configuration of external V1p05 VR rail
External V1P05 Rail Supported Configuration
**/
UINT8 PchFivrExtV1p05RailSupportedVoltageStates;
-/** Offset 0x04D4 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
+/** Offset 0x04B8 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
**/
UINT16 PchFivrExtV1p05RailVoltage;
-/** Offset 0x04D6 - External V1P05 Icc Max Value
+/** Offset 0x04BA - External V1P05 Icc Max Value
Granularity of this setting is 1mA and maximal possible value is 200mA
**/
UINT8 PchFivrExtV1p05RailIccMax;
-/** Offset 0x04D7 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
+/** Offset 0x04BB - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
**/
UINT8 PchFivrExtVnnRailEnabledStates;
-/** Offset 0x04D8 - Mask to enable the platform configuration of external Vnn VR rail
+/** Offset 0x04BC - Mask to enable the platform configuration of external Vnn VR rail
External Vnn Rail Supported Configuration
**/
UINT8 PchFivrExtVnnRailSupportedVoltageStates;
-/** Offset 0x04D9 - Reserved
+/** Offset 0x04BD - Reserved
**/
UINT8 Reserved15;
-/** Offset 0x04DA - External Vnn Voltage Value that will be used in S0ix/Sx states
+/** Offset 0x04BE - External Vnn Voltage Value that will be used in S0ix/Sx states
Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
**/
UINT16 PchFivrExtVnnRailVoltage;
-/** Offset 0x04DC - External Vnn Icc Max Value that will be used in S0ix/Sx states
+/** Offset 0x04C0 - External Vnn Icc Max Value that will be used in S0ix/Sx states
Granularity of this setting is 1mA and maximal possible value is 200mA
**/
UINT8 PchFivrExtVnnRailIccMax;
-/** Offset 0x04DD - Mask to enable the usage of external Vnn VR rail in Sx states
+/** Offset 0x04C1 - Mask to enable the usage of external Vnn VR rail in Sx states
Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in
Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5
**/
UINT8 PchFivrExtVnnRailSxEnabledStates;
-/** Offset 0x04DE - External Vnn Voltage Value that will be used in Sx states
+/** Offset 0x04C2 - External Vnn Voltage Value that will be used in Sx states
Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments
(0=0mV, 1=2.5mV, 2=5mV...)
**/
UINT16 PchFivrExtVnnRailSxVoltage;
-/** Offset 0x04E0 - External Vnn Icc Max Value that will be used in Sx states
+/** Offset 0x04C4 - External Vnn Icc Max Value that will be used in Sx states
Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
is 1mA and maximal possible value is 200mA
**/
UINT8 PchFivrExtVnnRailSxIccMax;
-/** Offset 0x04E1 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
+/** Offset 0x04C5 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
to low current mode voltage.
**/
UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime;
-/** Offset 0x04E2 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
+/** Offset 0x04C6 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
to retention mode voltage.
**/
UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime;
-/** Offset 0x04E3 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
+/** Offset 0x04C7 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
to retention mode voltage.
**/
UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime;
-/** Offset 0x04E4 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
+/** Offset 0x04C8 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
This field has 1us resolution. When value is 0 Transition to 0V is disabled.
**/
UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime;
-/** Offset 0x04E6 - PMC Debug Message Enable
+/** Offset 0x04CA - PMC Debug Message Enable
When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW
will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix
$EN_DIS
**/
UINT8 PmcDbgMsgEn;
-/** Offset 0x04E7 - Reserved
+/** Offset 0x04CB - Reserved
**/
UINT8 Reserved16;
-/** Offset 0x04E8 - Pointer of ChipsetInit Binary
+/** Offset 0x04CC - Pointer of ChipsetInit Binary
ChipsetInit Binary Pointer.
**/
UINT32 ChipsetInitBinPtr;
-/** Offset 0x04EC - Length of ChipsetInit Binary
+/** Offset 0x04D0 - Length of ChipsetInit Binary
ChipsetInit Binary Length.
**/
UINT32 ChipsetInitBinLen;
-/** Offset 0x04F0 - FIVR Dynamic Power Management
+/** Offset 0x04D4 - FIVR Dynamic Power Management
Enable/Disable FIVR Dynamic Power Management.
$EN_DIS
**/
UINT8 PchFivrDynPm;
-/** Offset 0x04F1 - Reserved
+/** Offset 0x04D5 - Reserved
**/
UINT8 Reserved17;
-/** Offset 0x04F2 - External V1P05 Icc Max Value
+/** Offset 0x04D6 - External V1P05 Icc Max Value
Granularity of this setting is 1mA and maximal possible value is 500mA
**/
UINT16 PchFivrExtV1p05RailIccMaximum;
-/** Offset 0x04F4 - External Vnn Icc Max Value that will be used in S0ix/Sx states
+/** Offset 0x04D8 - External Vnn Icc Max Value that will be used in S0ix/Sx states
Granularity of this setting is 1mA and maximal possible value is 500mA
**/
UINT16 PchFivrExtVnnRailIccMaximum;
-/** Offset 0x04F6 - External Vnn Icc Max Value that will be used in Sx states
+/** Offset 0x04DA - External Vnn Icc Max Value that will be used in Sx states
Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
is 1mA and maximal possible value is 500mA
**/
UINT16 PchFivrExtVnnRailSxIccMaximum;
-/** Offset 0x04F8 - Reserved
+/** Offset 0x04DC - Reserved
**/
UINT8 Reserved18[14];
-/** Offset 0x0506 - CNVi Configuration
+/** Offset 0x04EA - CNVi Configuration
This option allows for automatic detection of Connectivity Solution. [Auto Detection]
assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
0:Disable, 1:Auto
**/
UINT8 CnviMode;
-/** Offset 0x0507 - Reserved
+/** Offset 0x04EB - Reserved
**/
UINT8 Reserved19;
-/** Offset 0x0508 - CNVi BT Core
+/** Offset 0x04EC - CNVi BT Core
Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviBtCore;
-/** Offset 0x0509 - CNVi BT Audio Offload
+/** Offset 0x04ED - CNVi BT Audio Offload
Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviBtAudioOffload;
-/** Offset 0x050A - Reserved
+/** Offset 0x04EE - Reserved
**/
UINT8 Reserved20[2];
-/** Offset 0x050C - CNVi RF_RESET pin muxing
+/** Offset 0x04F0 - CNVi RF_RESET pin muxing
Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default)
or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
**/
UINT32 CnviRfResetPinMux;
-/** Offset 0x0510 - CNVi CLKREQ pin muxing
+/** Offset 0x04F4 - CNVi CLKREQ pin muxing
Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default)
or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in
GpioPins*.h.
**/
UINT32 CnviClkreqPinMux;
-/** Offset 0x0514 - Enable Host C10 reporting through eSPI
+/** Offset 0x04F8 - Enable Host C10 reporting through eSPI
Enable/disable Host C10 reporting to Device via eSPI Virtual Wire.
$EN_DIS
**/
UINT8 PchEspiHostC10ReportEnable;
-/** Offset 0x0515 - PCH USB2 PHY Power Gating enable
+/** Offset 0x04F9 - PCH USB2 PHY Power Gating enable
1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
Sus Well PG
$EN_DIS
**/
UINT8 PmcUsb2PhySusPgEnable;
-/** Offset 0x0516 - PCH USB OverCurrent mapping enable
+/** Offset 0x04FA - PCH USB OverCurrent mapping enable
1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
mapping allow for NOA usage of OC pins
$EN_DIS
**/
UINT8 PchUsbOverCurrentEnable;
-/** Offset 0x0517 - Espi Lgmr Memory Range decode
+/** Offset 0x04FB - Espi Lgmr Memory Range decode
This option enables or disables espi lgmr
$EN_DIS
**/
UINT8 PchEspiLgmrEnable;
-/** Offset 0x0518 - External V1P05 Control Ramp Timer value
+/** Offset 0x04FC - External V1P05 Control Ramp Timer value
Hold off time to be used when changing the v1p05_ctrl for external bypass value in us
**/
UINT8 PchFivrExtV1p05RailCtrlRampTmr;
-/** Offset 0x0519 - External VNN Control Ramp Timer value
+/** Offset 0x04FD - External VNN Control Ramp Timer value
Hold off time to be used when changing the vnn_ctrl for external bypass value in us
**/
UINT8 PchFivrExtVnnRailCtrlRampTmr;
-/** Offset 0x051A - Set SATA DEVSLP GPIO Reset Config
+/** Offset 0x04FE - Set SATA DEVSLP GPIO Reset Config
Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset,
0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte
for each port, byte0 for port0, byte1 for port1, and so on.
**/
UINT8 SataPortsDevSlpResetConfig[8];
-/** Offset 0x0522 - PCHHOT# pin
+/** Offset 0x0506 - PCHHOT# pin
Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PchHotEnable;
-/** Offset 0x0523 - SATA LED
+/** Offset 0x0507 - SATA LED
SATA LED indicating SATA controller activity. 0: disable, 1: enable
$EN_DIS
**/
UINT8 SataLedEnable;
-/** Offset 0x0524 - VRAlert# Pin
+/** Offset 0x0508 - VRAlert# Pin
When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PchPmVrAlert;
-/** Offset 0x0525 - AMT Switch
+/** Offset 0x0509 - AMT Switch
Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
$EN_DIS
**/
UINT8 AmtEnabled;
-/** Offset 0x0526 - WatchDog Timer Switch
+/** Offset 0x050A - WatchDog Timer Switch
Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting
is invalid if AmtEnabled is 0.
$EN_DIS
**/
UINT8 WatchDogEnabled;
-/** Offset 0x0527 - PET Progress
+/** Offset 0x050B - PET Progress
Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
PET Events. Setting is invalid if AmtEnabled is 0.
$EN_DIS
**/
UINT8 FwProgress;
-/** Offset 0x0528 - SOL Switch
+/** Offset 0x050C - SOL Switch
Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx.
Setting is invalid if AmtEnabled is 0.
$EN_DIS
**/
UINT8 AmtSolEnabled;
-/** Offset 0x0529 - Reserved
+/** Offset 0x050D - Reserved
**/
UINT8 Reserved21;
-/** Offset 0x052A - OS Timer
+/** Offset 0x050E - OS Timer
16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
**/
UINT16 WatchDogTimerOs;
-/** Offset 0x052C - BIOS Timer
+/** Offset 0x0510 - BIOS Timer
16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0.
**/
UINT16 WatchDogTimerBios;
-/** Offset 0x052E - Force MEBX execution
+/** Offset 0x0512 - Force MEBX execution
Enable/Disable. 0: Disable, 1: enable, Force MEBX execution.
$EN_DIS
**/
UINT8 ForcMebxSyncUp;
-/** Offset 0x052F - PCH PCIe root port connection type
+/** Offset 0x0513 - PCH PCIe root port connection type
0: built-in device, 1:slot
**/
UINT8 PcieRpSlotImplemented[28];
-/** Offset 0x054B - PCIE RP Access Control Services Extended Capability
+/** Offset 0x052F - PCIE RP Access Control Services Extended Capability
Enable/Disable PCIE RP Access Control Services Extended Capability
**/
UINT8 PcieRpAcsEnabled[28];
-/** Offset 0x0567 - PCIE RP Clock Power Management
+/** Offset 0x054B - PCIE RP Clock Power Management
Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
can still be controlled by L1 PM substates mechanism
**/
UINT8 PcieRpEnableCpm[28];
-/** Offset 0x0583 - Reserved
+/** Offset 0x0567 - Reserved
**/
UINT8 Reserved22;
-/** Offset 0x0584 - PCIE RP Detect Timeout Ms
+/** Offset 0x0568 - PCIE RP Detect Timeout Ms
The number of milliseconds within 0~65535 in reference code will wait for link to
exit Detect state for enabled ports before assuming there is no device and potentially
disabling the port.
**/
UINT16 PcieRpDetectTimeoutMs[24];
-/** Offset 0x05B4 - ModPHY SUS Power Domain Dynamic Gating
+/** Offset 0x0598 - ModPHY SUS Power Domain Dynamic Gating
Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
PCH-H. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PmcModPhySusPgEnable;
-/** Offset 0x05B5 - V1p05-PHY supply external FET control
+/** Offset 0x0599 - V1p05-PHY supply external FET control
Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY
supply. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PmcV1p05PhyExtFetControlEn;
-/** Offset 0x05B6 - V1p05-IS supply external FET control
+/** Offset 0x059A - V1p05-IS supply external FET control
Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS
supply. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PmcV1p05IsExtFetControlEn;
-/** Offset 0x05B7 - Enable/Disable PavpEnable
+/** Offset 0x059B - Enable/Disable PavpEnable
Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
$EN_DIS
**/
UINT8 PavpEnable;
-/** Offset 0x05B8 - Enable/Disable PeiGraphicsPeimInit
+/** Offset 0x059C - Enable/Disable PeiGraphicsPeimInit
<b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
Disable: FSP will NOT initialize the framebuffer.
$EN_DIS
**/
UINT8 PeiGraphicsPeimInit;
-/** Offset 0x05B9 - Enable D3 Hot in TCSS
+/** Offset 0x059D - Enable D3 Hot in TCSS
This policy will enable/disable D3 hot support in IOM
$EN_DIS
**/
UINT8 D3HotEnable;
-/** Offset 0x05BA - Enable or disable GNA device
+/** Offset 0x059E - Enable or disable GNA device
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 GnaEnable;
-/** Offset 0x05BB - Reserved
+/** Offset 0x059F - Reserved
**/
UINT8 Reserved23;
-/** Offset 0x05BC - TypeC port GPIO setting
+/** Offset 0x05A0 - TypeC port GPIO setting
GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
- in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl
- = AlderLake)
+ in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Mtl
+ = MeteorLake)
**/
UINT32 IomTypeCPortPadCfg[12];
-/** Offset 0x05EC - CPU USB3 Port Over Current Pin
+/** Offset 0x05D0 - CPU USB3 Port Over Current Pin
Describe the specific over current pin number of USBC Port N.
**/
UINT8 CpuUsb3OverCurrentPin[8];
-/** Offset 0x05F4 - Enable D3 Cold in TCSS
+/** Offset 0x05D8 - Enable D3 Cold in TCSS
This policy will enable/disable D3 cold support in IOM
$EN_DIS
**/
UINT8 D3ColdEnable;
-/** Offset 0x05F5 - Enable/Disable PCIe tunneling for USB4
+/** Offset 0x05D9 - Enable/Disable PCIe tunneling for USB4
Enable/Disable PCIe tunneling for USB4, default is enable
$EN_DIS
**/
UINT8 ITbtPcieTunnelingForUsb4;
-/** Offset 0x05F6 - Enable/Disable SkipFspGop
+/** Offset 0x05DA - Enable/Disable SkipFspGop
Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver
$EN_DIS
**/
UINT8 SkipFspGop;
-/** Offset 0x05F7 - Reserved
+/** Offset 0x05DB - Enable/Disable VPU Device
+ Enable(Default): Enable VPU Device, Disable: Disable VPU Device
+ $EN_DIS
**/
- UINT8 Reserved24;
+ UINT8 VpuEnable;
-/** Offset 0x05F8 - TC State in TCSS
+/** Offset 0x05DC - TC State in TCSS
This TC C-State Limit in IOM
**/
UINT8 TcCstateLimit;
-/** Offset 0x05F9 - Reserved
+/** Offset 0x05DD - Reserved
**/
- UINT8 Reserved25[3];
+ UINT8 Reserved24[3];
-/** Offset 0x05FC - Intel Graphics VBT (Video BIOS Table) Size
+/** Offset 0x05E0 - Intel Graphics VBT (Video BIOS Table) Size
Size of Internal Graphics VBT Image
**/
UINT32 VbtSize;
-/** Offset 0x0600 - Platform LID Status for LFP Displays.
+/** Offset 0x05E4 - Platform LID Status for LFP Displays.
LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
0: LidClosed, 1: LidOpen
**/
UINT8 LidStatus;
-/** Offset 0x0601 - Reserved
+/** Offset 0x05E5 - Reserved
**/
- UINT8 Reserved26[8];
+ UINT8 Reserved25[8];
-/** Offset 0x0609 - Enable VMD controller
+/** Offset 0x05ED - Enable VMD controller
Enable/disable to VMD controller.0: Disable(Default); 1: Enable
$EN_DIS
**/
UINT8 VmdEnable;
-/** Offset 0x060A - Enable VMD Global Mapping
+/** Offset 0x05EE - Enable VMD Global Mapping
Enable/disable to VMD controller.0: Disable(Default); 1: Enable
$EN_DIS
**/
UINT8 VmdGlobalMapping;
-/** Offset 0x060B - Map port under VMD
+/** Offset 0x05EF - Map port under VMD
Map/UnMap port under VMD
$EN_DIS
**/
UINT8 VmdPort[31];
-/** Offset 0x062A - Reserved
+/** Offset 0x060E - Reserved
**/
- UINT8 Reserved27[31];
+ UINT8 Reserved26[31];
-/** Offset 0x0649 - VMD Port Device
+/** Offset 0x062D - VMD Port Device
VMD Root port device number.
**/
UINT8 VmdPortDev[31];
-/** Offset 0x0668 - VMD Port Func
+/** Offset 0x064C - VMD Port Func
VMD Root port function number.
**/
UINT8 VmdPortFunc[31];
-/** Offset 0x0687 - Reserved
+/** Offset 0x066B - Reserved
**/
- UINT8 Reserved28;
+ UINT8 Reserved27;
-/** Offset 0x0688 - VMD Variable
+/** Offset 0x066C - VMD Variable
VMD Variable Pointer.
**/
UINT32 VmdVariablePtr;
-/** Offset 0x068C - Temporary CfgBar address for VMD
+/** Offset 0x0670 - Temporary CfgBar address for VMD
VMD Variable Pointer.
**/
UINT32 VmdCfgBarBase;
-/** Offset 0x0690 - Temporary MemBar1 address for VMD
+/** Offset 0x0674 - Temporary MemBar1 address for VMD
VMD Variable Pointer.
**/
UINT32 VmdMemBar1Base;
-/** Offset 0x0694 - Temporary MemBar2 address for VMD
+/** Offset 0x0678 - Temporary MemBar2 address for VMD
VMD Variable Pointer.
**/
UINT32 VmdMemBar2Base;
-/** Offset 0x0698 - Reserved
+/** Offset 0x067C - Reserved
**/
- UINT8 Reserved29;
+ UINT8 Reserved28;
-/** Offset 0x0699 - Enable/Disable PMC-PD Solution
+/** Offset 0x067D - Enable/Disable PMC-PD Solution
This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
$EN_DIS
**/
UINT8 PmcPdEnable;
-/** Offset 0x069A - TCSS Aux Orientation Override Enable
+/** Offset 0x067E - TCSS Aux Orientation Override Enable
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
**/
UINT16 TcssAuxOri;
-/** Offset 0x069C - TCSS HSL Orientation Override Enable
+/** Offset 0x0680 - TCSS HSL Orientation Override Enable
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
**/
UINT16 TcssHslOri;
-/** Offset 0x069E - USB override in IOM
+/** Offset 0x0682 - USB override in IOM
This policy will enable/disable USB Connect override in IOM
$EN_DIS
**/
UINT8 UsbOverride;
-/** Offset 0x069F - ITBT Root Port Enable
+/** Offset 0x0683 - ITBT Root Port Enable
ITBT Root Port Enable, 0:Disable, 1:Enable
0:Disable, 1:Enable
**/
UINT8 ITbtPcieRootPortEn[4];
-/** Offset 0x06A3 - TCSS USB Port Enable
+/** Offset 0x0687 - TCSS USB Port Enable
Bits 0, 1, ... max Type C port control enables
**/
UINT8 UsbTcPortEn;
-/** Offset 0x06A4 - ITBTForcePowerOn Timeout value
+/** Offset 0x0688 - ITBTForcePowerOn Timeout value
ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000.
100 = 100 ms.
**/
UINT16 ITbtForcePowerOnTimeoutInMs;
-/** Offset 0x06A6 - ITbtConnectTopology Timeout value
+/** Offset 0x068A - ITbtConnectTopology Timeout value
ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
is 0-10000. 100 = 100 ms.
**/
UINT16 ITbtConnectTopologyTimeoutInMs;
-/** Offset 0x06A8 - VCCST request for IOM
+/** Offset 0x068C - VCCST request for IOM
This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5
$EN_DIS
**/
UINT8 VccSt;
-/** Offset 0x06A9 - Reserved
+/** Offset 0x068D - Reserved
**/
- UINT8 Reserved30;
+ UINT8 Reserved29;
-/** Offset 0x06AA - ITBT DMA LTR
+/** Offset 0x068E - ITBT DMA LTR
TCSS DMA1, DMA2 LTR value
**/
UINT16 ITbtDmaLtr[2];
-/** Offset 0x06AE - Reserved
+/** Offset 0x0692 - Reserved
**/
- UINT8 Reserved31;
+ UINT8 Reserved30;
-/** Offset 0x06AF - Enable/Disable PTM
+/** Offset 0x0693 - Enable/Disable PTM
This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
$EN_DIS
**/
UINT8 PtmEnabled[4];
-/** Offset 0x06B3 - PCIE RP Ltr Enable
+/** Offset 0x0697 - PCIE RP Ltr Enable
Latency Tolerance Reporting Mechanism.
**/
UINT8 SaPcieItbtRpLtrEnable[4];
-/** Offset 0x06B7 - PCIE RP Snoop Latency Override Mode
+/** Offset 0x069B - PCIE RP Snoop Latency Override Mode
Latency Tolerance Reporting, Snoop Latency Override Mode.
**/
UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4];
-/** Offset 0x06BB - PCIE RP Snoop Latency Override Multiplier
+/** Offset 0x069F - PCIE RP Snoop Latency Override Multiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
**/
UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4];
-/** Offset 0x06BF - Reserved
+/** Offset 0x06A3 - Reserved
**/
- UINT8 Reserved32;
+ UINT8 Reserved31;
-/** Offset 0x06C0 - PCIE RP Snoop Latency Override Value
+/** Offset 0x06A4 - PCIE RP Snoop Latency Override Value
Latency Tolerance Reporting, Snoop Latency Override Value.
**/
UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4];
-/** Offset 0x06C8 - PCIE RP Non Snoop Latency Override Mode
+/** Offset 0x06AC - PCIE RP Non Snoop Latency Override Mode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
**/
UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4];
-/** Offset 0x06CC - PCIE RP Non Snoop Latency Override Multiplier
+/** Offset 0x06B0 - PCIE RP Non Snoop Latency Override Multiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
**/
UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4];
-/** Offset 0x06D0 - PCIE RP Non Snoop Latency Override Value
+/** Offset 0x06B4 - PCIE RP Non Snoop Latency Override Value
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
**/
UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4];
-/** Offset 0x06D8 - Force LTR Override
+/** Offset 0x06BC - Force LTR Override
Force LTR Override.
**/
UINT8 SaPcieItbtRpForceLtrOverride[4];
-/** Offset 0x06DC - PCIE RP Ltr Config Lock
+/** Offset 0x06C0 - PCIE RP Ltr Config Lock
0: Disable; 1: Enable.
**/
UINT8 SaPcieItbtRpLtrConfigLock[4];
-/** Offset 0x06E0 - Enable or Disable TXT
+/** Offset 0x06C4 - Enable or Disable TXT
Enables utilization of additional hardware capabilities provided by Intel (R) Trusted
Execution Technology. Changes require a full power cycle to take effect. <b>0:
Disable</b>, 1: Enable.
@@ -1325,27 +1328,27 @@ typedef struct {
**/
UINT8 TxtEnable;
-/** Offset 0x06E1 - Reserved
+/** Offset 0x06C5 - Reserved
**/
- UINT8 Reserved33[3];
+ UINT8 Reserved32[3];
-/** Offset 0x06E4 - CpuBistData
+/** Offset 0x06C8 - CpuBistData
Pointer CPU BIST Data
**/
UINT32 CpuBistData;
-/** Offset 0x06E8 - CpuMpPpi
+/** Offset 0x06CC - CpuMpPpi
<b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
If not NULL, FSP will use the boot loader's implementation of multiprocessing.
See section 5.1.4 of the FSP Integration Guide for more details.
**/
UINT32 CpuMpPpi;
-/** Offset 0x06EC - Reserved
+/** Offset 0x06D0 - Reserved
**/
- UINT8 Reserved34[14];
+ UINT8 Reserved33[14];
-/** Offset 0x06FA - PpinSupport to view Protected Processor Inventory Number
+/** Offset 0x06DE - PpinSupport to view Protected Processor Inventory Number
PPIN Feature Support to view Protected Processor Inventory Number. Disable to turn
off this feature. When 'PPIN Enable Mode' is selected, this shows second option
where feature can be enabled based on EOM (End of Manufacturing) flag or it is
@@ -1354,698 +1357,708 @@ typedef struct {
**/
UINT8 PpinSupport;
-/** Offset 0x06FB - Reserved
+/** Offset 0x06DF - Reserved
**/
- UINT8 Reserved35;
+ UINT8 Reserved34;
-/** Offset 0x06FC - Smbios Type4 Max Speed Override
+/** Offset 0x06E0 - Smbios Type4 Max Speed Override
Provide the option for platform to override the MaxSpeed field of Smbios Type 4.
If this value is not zero, it dominates the field.
**/
UINT16 SmbiosType4MaxSpeedOverride;
-/** Offset 0x06FE - Advanced Encryption Standard (AES) feature
+/** Offset 0x06E2 - Advanced Encryption Standard (AES) feature
Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
$EN_DIS
**/
UINT8 AesEnable;
-/** Offset 0x06FF - AvxDisable
+/** Offset 0x06E3 - AvxDisable
Enable/Disable the AVX and AVX2 Instructions
0: Enable, 1: Disable
**/
UINT8 AvxDisable;
-/** Offset 0x0700 - Reserved
+/** Offset 0x06E4 - Reserved
**/
- UINT8 Reserved36[49];
+ UINT8 Reserved35[48];
-/** Offset 0x0731 - Enable Power Optimizer
+/** Offset 0x0714 - Enable Power Optimizer
Enable DMI Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 PchPwrOptEnable;
-/** Offset 0x0732 - PCH Flash Protection Ranges Write Enble
+/** Offset 0x0715 - PCH Flash Protection Ranges Write Enble
Write or erase is blocked by hardware.
**/
UINT8 PchWriteProtectionEnable[5];
-/** Offset 0x0737 - PCH Flash Protection Ranges Read Enble
+/** Offset 0x071A - PCH Flash Protection Ranges Read Enble
Read is blocked by hardware.
**/
UINT8 PchReadProtectionEnable[5];
-/** Offset 0x073C - PCH Protect Range Limit
+/** Offset 0x071F - Reserved
+**/
+ UINT8 Reserved36;
+
+/** Offset 0x0720 - PCH Protect Range Limit
Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
limit comparison.
**/
UINT16 PchProtectedRangeLimit[5];
-/** Offset 0x0746 - PCH Protect Range Base
+/** Offset 0x072A - PCH Protect Range Base
Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
**/
UINT16 PchProtectedRangeBase[5];
-/** Offset 0x0750 - Enable Pme
+/** Offset 0x0734 - Enable Pme
Enable Azalia wake-on-ring.
$EN_DIS
**/
UINT8 PchHdaPme;
-/** Offset 0x0751 - HD Audio Link Frequency
+/** Offset 0x0735 - HD Audio Link Frequency
HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
0: 6MHz, 1: 12MHz, 2: 24MHz
**/
UINT8 PchHdaLinkFrequency;
-/** Offset 0x0752 - Enable PCH ISH SPI Cs0 pins assigned
+/** Offset 0x0736 - Enable PCH ISH SPI Cs0 pins assigned
Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshSpiCs0Enable[1];
-/** Offset 0x0753 - Enable PCH Io Apic Entry 24-119
+/** Offset 0x0737 - Enable PCH Io Apic Entry 24-119
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIoApicEntry24_119;
-/** Offset 0x0754 - PCH Io Apic ID
+/** Offset 0x0738 - PCH Io Apic ID
This member determines IOAPIC ID. Default is 0x02.
**/
UINT8 PchIoApicId;
-/** Offset 0x0755 - Enable PCH ISH SPI pins assigned
+/** Offset 0x0739 - Enable PCH ISH SPI pins assigned
Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshSpiEnable[1];
-/** Offset 0x0756 - Enable PCH ISH UART pins assigned
+/** Offset 0x073A - Enable PCH ISH UART pins assigned
Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshUartEnable[2];
-/** Offset 0x0758 - Enable PCH ISH I2C pins assigned
+/** Offset 0x073C - Enable PCH ISH I2C pins assigned
Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshI2cEnable[3];
-/** Offset 0x075B - Reserved
+/** Offset 0x073F - Enable PCH ISH I3C pins assigned
+ Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
- UINT8 Reserved37;
+ UINT8 PchIshI3cEnable;
-/** Offset 0x075C - Enable PCH ISH GP pins assigned
+/** Offset 0x0740 - Enable PCH ISH GP pins assigned
Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshGpEnable[12];
-/** Offset 0x0768 - PCH ISH PDT Unlock Msg
+/** Offset 0x074C - PCH ISH PDT Unlock Msg
0: False; 1: True.
$EN_DIS
**/
UINT8 PchIshPdtUnlock;
-/** Offset 0x0769 - Reserved
+/** Offset 0x074D - Reserved
**/
- UINT8 Reserved38;
+ UINT8 Reserved37;
-/** Offset 0x076A - Enable PCH Lan LTR capabilty of PCH internal LAN
+/** Offset 0x074E - Enable PCH Lan LTR capabilty of PCH internal LAN
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchLanLtrEnable;
-/** Offset 0x076B - Enable LOCKDOWN BIOS LOCK
+/** Offset 0x074F - Enable LOCKDOWN BIOS LOCK
Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
protection.
$EN_DIS
**/
UINT8 PchLockDownBiosLock;
-/** Offset 0x076C - PCH Compatibility Revision ID
+/** Offset 0x0750 - PCH Compatibility Revision ID
This member describes whether or not the CRID feature of PCH should be enabled.
$EN_DIS
**/
UINT8 PchCrid;
-/** Offset 0x076D - RTC BIOS Interface Lock
+/** Offset 0x0751 - RTC BIOS Interface Lock
Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed.
$EN_DIS
**/
UINT8 RtcBiosInterfaceLock;
-/** Offset 0x076E - RTC Cmos Memory Lock
+/** Offset 0x0752 - RTC Cmos Memory Lock
Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
and and lower 128-byte bank of RTC RAM.
$EN_DIS
**/
UINT8 RtcMemoryLock;
-/** Offset 0x076F - Enable PCIE RP HotPlug
+/** Offset 0x0753 - Enable PCIE RP HotPlug
Indicate whether the root port is hot plug available.
**/
UINT8 PcieRpHotPlug[28];
-/** Offset 0x078B - Enable PCIE RP Pm Sci
+/** Offset 0x076F - Enable PCIE RP Pm Sci
Indicate whether the root port power manager SCI is enabled.
**/
UINT8 PcieRpPmSci[28];
-/** Offset 0x07A7 - Enable PCIE RP Transmitter Half Swing
+/** Offset 0x078B - Enable PCIE RP Transmitter Half Swing
Indicate whether the Transmitter Half Swing is enabled.
**/
UINT8 PcieRpTransmitterHalfSwing[28];
-/** Offset 0x07C3 - Enable PCIE RP Clk Req Detect
+/** Offset 0x07A7 - Enable PCIE RP Clk Req Detect
Probe CLKREQ# signal before enabling CLKREQ# based power management.
**/
UINT8 PcieRpClkReqDetect[28];
-/** Offset 0x07DF - PCIE RP Advanced Error Report
+/** Offset 0x07C3 - PCIE RP Advanced Error Report
Indicate whether the Advanced Error Reporting is enabled.
**/
UINT8 PcieRpAdvancedErrorReporting[28];
-/** Offset 0x07FB - PCIE RP Unsupported Request Report
+/** Offset 0x07DF - PCIE RP Unsupported Request Report
Indicate whether the Unsupported Request Report is enabled.
**/
UINT8 PcieRpUnsupportedRequestReport[28];
-/** Offset 0x0817 - PCIE RP Fatal Error Report
+/** Offset 0x07FB - PCIE RP Fatal Error Report
Indicate whether the Fatal Error Report is enabled.
**/
UINT8 PcieRpFatalErrorReport[28];
-/** Offset 0x0833 - PCIE RP No Fatal Error Report
+/** Offset 0x0817 - PCIE RP No Fatal Error Report
Indicate whether the No Fatal Error Report is enabled.
**/
UINT8 PcieRpNoFatalErrorReport[28];
-/** Offset 0x084F - PCIE RP Correctable Error Report
+/** Offset 0x0833 - PCIE RP Correctable Error Report
Indicate whether the Correctable Error Report is enabled.
**/
UINT8 PcieRpCorrectableErrorReport[28];
-/** Offset 0x086B - PCIE RP System Error On Fatal Error
+/** Offset 0x084F - PCIE RP System Error On Fatal Error
Indicate whether the System Error on Fatal Error is enabled.
**/
UINT8 PcieRpSystemErrorOnFatalError[28];
-/** Offset 0x0887 - PCIE RP System Error On Non Fatal Error
+/** Offset 0x086B - PCIE RP System Error On Non Fatal Error
Indicate whether the System Error on Non Fatal Error is enabled.
**/
UINT8 PcieRpSystemErrorOnNonFatalError[28];
-/** Offset 0x08A3 - PCIE RP System Error On Correctable Error
+/** Offset 0x0887 - PCIE RP System Error On Correctable Error
Indicate whether the System Error on Correctable Error is enabled.
**/
UINT8 PcieRpSystemErrorOnCorrectableError[28];
-/** Offset 0x08BF - PCIE RP Max Payload
+/** Offset 0x08A3 - PCIE RP Max Payload
Max Payload Size supported, Default 64B, see enum PCH_PCIE_MAX_PAYLOAD.
**/
UINT8 PcieRpMaxPayload[28];
-/** Offset 0x08DB - Reserved
+/** Offset 0x08BF - Touch Host Controller Assignment
+ Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1
+**/
+ UINT8 ThcAssignment[2];
+
+/** Offset 0x08C1 - Reserved
**/
- UINT8 Reserved39[121];
+ UINT8 Reserved38[123];
-/** Offset 0x0954 - PCIE RP Pcie Speed
+/** Offset 0x093C - PCIE RP Pcie Speed
Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
PCIE_SPEED).
**/
UINT8 PcieRpPcieSpeed[28];
-/** Offset 0x0970 - PCIE RP Physical Slot Number
+/** Offset 0x0958 - PCIE RP Physical Slot Number
Indicates the slot number for the root port. Default is the value as root port index.
**/
UINT8 PcieRpPhysicalSlotNumber[28];
-/** Offset 0x098C - PCIE RP Completion Timeout
+/** Offset 0x0974 - PCIE RP Completion Timeout
The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
**/
UINT8 PcieRpCompletionTimeout[28];
-/** Offset 0x09A8 - PCIE RP Aspm
+/** Offset 0x0990 - PCIE RP Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
PchPcieAspmAutoConfig.
**/
UINT8 PcieRpAspm[28];
-/** Offset 0x09C4 - PCIE RP L1 Substates
+/** Offset 0x09AC - PCIE RP L1 Substates
The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
Default is PchPcieL1SubstatesL1_1_2.
**/
UINT8 PcieRpL1Substates[28];
-/** Offset 0x09E0 - PCIE RP Ltr Enable
+/** Offset 0x09C8 - PCIE RP Ltr Enable
Latency Tolerance Reporting Mechanism.
**/
UINT8 PcieRpLtrEnable[28];
-/** Offset 0x09FC - PCIE RP Ltr Config Lock
+/** Offset 0x09E4 - PCIE RP Ltr Config Lock
0: Disable; 1: Enable.
**/
UINT8 PcieRpLtrConfigLock[28];
-/** Offset 0x0A18 - PCIE RP override default settings for EQ
+/** Offset 0x0A00 - PCIE RP override default settings for EQ
Choose PCIe EQ method
$EN_DIS
**/
UINT8 PcieEqOverrideDefault[12];
-/** Offset 0x0A24 - Reserved
+/** Offset 0x0A0C - Reserved
**/
- UINT8 Reserved40[1574];
+ UINT8 Reserved39[1574];
-/** Offset 0x104A - PCIE RP Enable Peer Memory Write
+/** Offset 0x1032 - PCIE RP Enable Peer Memory Write
This member describes whether Peer Memory Writes are enabled on the platform.
$EN_DIS
**/
UINT8 PcieEnablePeerMemoryWrite[12];
-/** Offset 0x1056 - PCIE Compliance Test Mode
+/** Offset 0x103E - PCIE Compliance Test Mode
Compliance Test Mode shall be enabled when using Compliance Load Board.
$EN_DIS
**/
UINT8 PcieComplianceTestMode;
-/** Offset 0x1057 - PCIE Rp Function Swap
+/** Offset 0x103F - PCIE Rp Function Swap
Allows BIOS to use root port function number swapping when root port of function
0 is disabled.
$EN_DIS
**/
UINT8 PcieRpFunctionSwap;
-/** Offset 0x1058 - Reserved
+/** Offset 0x1040 - Reserved
**/
- UINT8 Reserved41;
+ UINT8 Reserved40;
-/** Offset 0x1059 - PCH Pm PME_B0_S5_DIS
+/** Offset 0x1041 - PCH Pm PME_B0_S5_DIS
When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
$EN_DIS
**/
UINT8 PchPmPmeB0S5Dis;
-/** Offset 0x105A - PCIE IMR
+/** Offset 0x1042 - PCIE IMR
Enables Isolated Memory Region for PCIe.
$EN_DIS
**/
UINT8 PcieRpImrEnabled;
-/** Offset 0x105B - PCIE IMR port number
+/** Offset 0x1043 - PCIE IMR port number
Selects PCIE root port number for IMR feature.
**/
UINT8 PcieRpImrSelection;
-/** Offset 0x105C - PCH Pm Wol Enable Override
+/** Offset 0x1044 - PCH Pm Wol Enable Override
Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
$EN_DIS
**/
UINT8 PchPmWolEnableOverride;
-/** Offset 0x105D - PCH Pm WoW lan Enable
+/** Offset 0x1045 - PCH Pm WoW lan Enable
Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
$EN_DIS
**/
UINT8 PchPmWoWlanEnable;
-/** Offset 0x105E - PCH Pm Slp S3 Min Assert
+/** Offset 0x1046 - PCH Pm Slp S3 Min Assert
SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
**/
UINT8 PchPmSlpS3MinAssert;
-/** Offset 0x105F - PCH Pm Slp S4 Min Assert
+/** Offset 0x1047 - PCH Pm Slp S4 Min Assert
SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
**/
UINT8 PchPmSlpS4MinAssert;
-/** Offset 0x1060 - PCH Pm Slp Sus Min Assert
+/** Offset 0x1048 - PCH Pm Slp Sus Min Assert
SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
**/
UINT8 PchPmSlpSusMinAssert;
-/** Offset 0x1061 - PCH Pm Slp A Min Assert
+/** Offset 0x1049 - PCH Pm Slp A Min Assert
SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
**/
UINT8 PchPmSlpAMinAssert;
-/** Offset 0x1062 - USB Overcurrent Override for VISA
+/** Offset 0x104A - USB Overcurrent Override for VISA
This option overrides USB Over Current enablement state that USB OC will be disabled
after enabling this option. Enable when VISA pin is muxed with USB OC
$EN_DIS
**/
UINT8 PchEnableDbcObs;
-/** Offset 0x1063 - PCH Pm Slp Strch Sus Up
+/** Offset 0x104B - PCH Pm Slp Strch Sus Up
Enable SLP_X Stretching After SUS Well Power Up.
$EN_DIS
**/
UINT8 PchPmSlpStrchSusUp;
-/** Offset 0x1064 - PCH Pm Slp Lan Low Dc
+/** Offset 0x104C - PCH Pm Slp Lan Low Dc
Enable/Disable SLP_LAN# Low on DC Power.
$EN_DIS
**/
UINT8 PchPmSlpLanLowDc;
-/** Offset 0x1065 - PCH Pm Pwr Btn Override Period
+/** Offset 0x104D - PCH Pm Pwr Btn Override Period
PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
**/
UINT8 PchPmPwrBtnOverridePeriod;
-/** Offset 0x1066 - PCH Pm Disable Native Power Button
+/** Offset 0x104E - PCH Pm Disable Native Power Button
Power button native mode disable.
$EN_DIS
**/
UINT8 PchPmDisableNativePowerButton;
-/** Offset 0x1067 - PCH Pm ME_WAKE_STS
+/** Offset 0x104F - PCH Pm ME_WAKE_STS
Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
$EN_DIS
**/
UINT8 PchPmMeWakeSts;
-/** Offset 0x1068 - PCH Pm WOL_OVR_WK_STS
+/** Offset 0x1050 - PCH Pm WOL_OVR_WK_STS
Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
$EN_DIS
**/
UINT8 PchPmWolOvrWkSts;
-/** Offset 0x1069 - PCH Pm Reset Power Cycle Duration
+/** Offset 0x1051 - PCH Pm Reset Power Cycle Duration
Could be customized in the unit of second. Please refer to EDS for all support settings.
0 is default, 1 is 1 second, 2 is 2 seconds, ...
**/
UINT8 PchPmPwrCycDur;
-/** Offset 0x106A - PCH Pm Pcie Pll Ssc
+/** Offset 0x1052 - PCH Pm Pcie Pll Ssc
Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
BIOS override.
**/
UINT8 PchPmPciePllSsc;
-/** Offset 0x106B - PCH Legacy IO Low Latency Enable
+/** Offset 0x1053 - PCH Legacy IO Low Latency Enable
Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable
$EN_DIS
**/
UINT8 PchLegacyIoLowLatency;
-/** Offset 0x106C - PCH Sata Pwr Opt Enable
+/** Offset 0x1054 - PCH Sata Pwr Opt Enable
SATA Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 SataPwrOptEnable;
-/** Offset 0x106D - PCH Sata eSATA Speed Limit
+/** Offset 0x1055 - PCH Sata eSATA Speed Limit
When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
$EN_DIS
**/
UINT8 EsataSpeedLimit;
-/** Offset 0x106E - PCH Sata Speed Limit
+/** Offset 0x1056 - PCH Sata Speed Limit
Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
**/
UINT8 SataSpeedLimit;
-/** Offset 0x106F - Enable SATA Port HotPlug
+/** Offset 0x1057 - Enable SATA Port HotPlug
Enable SATA Port HotPlug.
**/
UINT8 SataPortsHotPlug[8];
-/** Offset 0x1077 - Enable SATA Port Interlock Sw
+/** Offset 0x105F - Enable SATA Port Interlock Sw
Enable SATA Port Interlock Sw.
**/
UINT8 SataPortsInterlockSw[8];
-/** Offset 0x107F - Enable SATA Port External
+/** Offset 0x1067 - Enable SATA Port External
Enable SATA Port External.
**/
UINT8 SataPortsExternal[8];
-/** Offset 0x1087 - Enable SATA Port SpinUp
+/** Offset 0x106F - Enable SATA Port SpinUp
Enable the COMRESET initialization Sequence to the device.
**/
UINT8 SataPortsSpinUp[8];
-/** Offset 0x108F - Enable SATA Port Solid State Drive
+/** Offset 0x1077 - Enable SATA Port Solid State Drive
0: HDD; 1: SSD.
**/
UINT8 SataPortsSolidStateDrive[8];
-/** Offset 0x1097 - Enable SATA Port Enable Dito Config
+/** Offset 0x107F - Enable SATA Port Enable Dito Config
Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
**/
UINT8 SataPortsEnableDitoConfig[8];
-/** Offset 0x109F - Enable SATA Port DmVal
+/** Offset 0x1087 - Enable SATA Port DmVal
DITO multiplier. Default is 15.
**/
UINT8 SataPortsDmVal[8];
-/** Offset 0x10A7 - Reserved
+/** Offset 0x108F - Reserved
**/
- UINT8 Reserved42;
+ UINT8 Reserved41;
-/** Offset 0x10A8 - Enable SATA Port DmVal
+/** Offset 0x1090 - Enable SATA Port DmVal
DEVSLP Idle Timeout (DITO), Default is 625.
**/
UINT16 SataPortsDitoVal[8];
-/** Offset 0x10B8 - Enable SATA Port ZpOdd
+/** Offset 0x10A0 - Enable SATA Port ZpOdd
Support zero power ODD.
**/
UINT8 SataPortsZpOdd[8];
-/** Offset 0x10C0 - PCH Sata Rst Raid Alternate Id
+/** Offset 0x10A8 - PCH Sata Rst Raid Alternate Id
Enable RAID Alternate ID.
$EN_DIS
**/
UINT8 SataRstRaidDeviceId;
-/** Offset 0x10C1 - PCH Sata Rst Pcie Storage Remap enable
+/** Offset 0x10A9 - PCH Sata Rst Pcie Storage Remap enable
Enable Intel RST for PCIe Storage remapping.
**/
UINT8 SataRstPcieEnable[3];
-/** Offset 0x10C4 - PCH Sata Rst Pcie Storage Port
+/** Offset 0x10AC - PCH Sata Rst Pcie Storage Port
Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
**/
UINT8 SataRstPcieStoragePort[3];
-/** Offset 0x10C7 - PCH Sata Rst Pcie Device Reset Delay
+/** Offset 0x10AF - PCH Sata Rst Pcie Device Reset Delay
PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
**/
UINT8 SataRstPcieDeviceResetDelay[3];
-/** Offset 0x10CA - UFS enable/disable
+/** Offset 0x10B2 - UFS enable/disable
PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
$EN_DIS
**/
UINT8 UfsEnable[2];
-/** Offset 0x10CC - Reserved
+/** Offset 0x10B4 - Reserved
**/
- UINT8 Reserved43[2];
+ UINT8 Reserved42[2];
-/** Offset 0x10CE - IEH Mode
+/** Offset 0x10B6 - IEH Mode
Integrated Error Handler Mode, 0: Bypass, 1: Enable
0: Bypass, 1:Enable
**/
UINT8 IehMode;
-/** Offset 0x10CF - Reserved
+/** Offset 0x10B7 - Reserved
**/
- UINT8 Reserved44[11];
+ UINT8 Reserved43[11];
-/** Offset 0x10DA - PCH Thermal Throttling Custimized T0Level Value
+/** Offset 0x10C2 - PCH Thermal Throttling Custimized T0Level Value
Custimized T0Level value.
**/
UINT16 PchT0Level;
-/** Offset 0x10DC - PCH Thermal Throttling Custimized T1Level Value
+/** Offset 0x10C4 - PCH Thermal Throttling Custimized T1Level Value
Custimized T1Level value.
**/
UINT16 PchT1Level;
-/** Offset 0x10DE - PCH Thermal Throttling Custimized T2Level Value
+/** Offset 0x10C6 - PCH Thermal Throttling Custimized T2Level Value
Custimized T2Level value.
**/
UINT16 PchT2Level;
-/** Offset 0x10E0 - Enable PCH Thermal Throttle
+/** Offset 0x10C8 - Enable PCH Thermal Throttle
Enable thermal throttle function.
$EN_DIS
**/
UINT8 PchTTEnable;
-/** Offset 0x10E1 - PCH PMSync State 13
+/** Offset 0x10C9 - PCH PMSync State 13
When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
at least T2 state.
$EN_DIS
**/
UINT8 PchTTState13Enable;
-/** Offset 0x10E2 - PCH Thermal Throttle Lock
+/** Offset 0x10CA - PCH Thermal Throttle Lock
Thermal Throttle Lock.
$EN_DIS
**/
UINT8 PchTTLock;
-/** Offset 0x10E3 - Reserved
+/** Offset 0x10CB - Reserved
**/
- UINT8 Reserved45[9];
+ UINT8 Reserved44[9];
-/** Offset 0x10EC - Enable PCH Cross Throttling
+/** Offset 0x10D4 - Enable PCH Cross Throttling
Enable/Disable PCH Cross Throttling
$EN_DIS
**/
UINT8 TTCrossThrottling;
-/** Offset 0x10ED - DMI Thermal Sensor Autonomous Width Enable
+/** Offset 0x10D5 - DMI Thermal Sensor Autonomous Width Enable
DMI Thermal Sensor Autonomous Width Enable.
$EN_DIS
**/
UINT8 PchDmiTsawEn;
-/** Offset 0x10EE - DMI Thermal Sensor Suggested Setting
+/** Offset 0x10D6 - DMI Thermal Sensor Suggested Setting
DMT thermal sensor suggested representative values.
$EN_DIS
**/
UINT8 DmiSuggestedSetting;
-/** Offset 0x10EF - Thermal Sensor 0 Target Width
+/** Offset 0x10D7 - Thermal Sensor 0 Target Width
Thermal Sensor 0 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS0TW;
-/** Offset 0x10F0 - Thermal Sensor 1 Target Width
+/** Offset 0x10D8 - Thermal Sensor 1 Target Width
Thermal Sensor 1 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS1TW;
-/** Offset 0x10F1 - Thermal Sensor 2 Target Width
+/** Offset 0x10D9 - Thermal Sensor 2 Target Width
Thermal Sensor 2 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS2TW;
-/** Offset 0x10F2 - Thermal Sensor 3 Target Width
+/** Offset 0x10DA - Thermal Sensor 3 Target Width
Thermal Sensor 3 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS3TW;
-/** Offset 0x10F3 - Port 0 T1 Multipler
+/** Offset 0x10DB - Port 0 T1 Multipler
Port 0 T1 Multipler.
**/
UINT8 SataP0T1M;
-/** Offset 0x10F4 - Port 0 T2 Multipler
+/** Offset 0x10DC - Port 0 T2 Multipler
Port 0 T2 Multipler.
**/
UINT8 SataP0T2M;
-/** Offset 0x10F5 - Port 0 T3 Multipler
+/** Offset 0x10DD - Port 0 T3 Multipler
Port 0 T3 Multipler.
**/
UINT8 SataP0T3M;
-/** Offset 0x10F6 - Port 0 Tdispatch
+/** Offset 0x10DE - Port 0 Tdispatch
Port 0 Tdispatch.
**/
UINT8 SataP0TDisp;
-/** Offset 0x10F7 - Port 1 T1 Multipler
+/** Offset 0x10DF - Port 1 T1 Multipler
Port 1 T1 Multipler.
**/
UINT8 SataP1T1M;
-/** Offset 0x10F8 - Port 1 T2 Multipler
+/** Offset 0x10E0 - Port 1 T2 Multipler
Port 1 T2 Multipler.
**/
UINT8 SataP1T2M;
-/** Offset 0x10F9 - Port 1 T3 Multipler
+/** Offset 0x10E1 - Port 1 T3 Multipler
Port 1 T3 Multipler.
**/
UINT8 SataP1T3M;
-/** Offset 0x10FA - Port 1 Tdispatch
+/** Offset 0x10E2 - Port 1 Tdispatch
Port 1 Tdispatch.
**/
UINT8 SataP1TDisp;
-/** Offset 0x10FB - Port 0 Tinactive
+/** Offset 0x10E3 - Port 0 Tinactive
Port 0 Tinactive.
**/
UINT8 SataP0Tinact;
-/** Offset 0x10FC - Port 0 Alternate Fast Init Tdispatch
+/** Offset 0x10E4 - Port 0 Alternate Fast Init Tdispatch
Port 0 Alternate Fast Init Tdispatch.
$EN_DIS
**/
UINT8 SataP0TDispFinit;
-/** Offset 0x10FD - Port 1 Tinactive
+/** Offset 0x10E5 - Port 1 Tinactive
Port 1 Tinactive.
**/
UINT8 SataP1Tinact;
-/** Offset 0x10FE - Port 1 Alternate Fast Init Tdispatch
+/** Offset 0x10E6 - Port 1 Alternate Fast Init Tdispatch
Port 1 Alternate Fast Init Tdispatch.
$EN_DIS
**/
UINT8 SataP1TDispFinit;
-/** Offset 0x10FF - Sata Thermal Throttling Suggested Setting
+/** Offset 0x10E7 - Sata Thermal Throttling Suggested Setting
Sata Thermal Throttling Suggested Setting.
$EN_DIS
**/
UINT8 SataThermalSuggestedSetting;
-/** Offset 0x1100 - Thermal Device Temperature
+/** Offset 0x10E8 - Thermal Device Temperature
Decides the temperature.
**/
UINT16 PchTemperatureHotLevel;
-/** Offset 0x1102 - USB2 Port Over Current Pin
+/** Offset 0x10EA - USB2 Port Over Current Pin
Describe the specific over current pin number of USB 2.0 Port N.
**/
UINT8 Usb2OverCurrentPin[16];
-/** Offset 0x1112 - USB3 Port Over Current Pin
+/** Offset 0x10FA - USB3 Port Over Current Pin
Describe the specific over current pin number of USB 3.0 Port N.
**/
UINT8 Usb3OverCurrentPin[10];
-/** Offset 0x111C - Enable xHCI LTR override
+/** Offset 0x1104 - Enable xHCI LTR override
Enables override of recommended LTR values for xHCI
$EN_DIS
**/
UINT8 PchUsbLtrOverrideEnable;
-/** Offset 0x111D - Reserved
+/** Offset 0x1105 - Reserved
**/
- UINT8 Reserved46[3];
+ UINT8 Reserved45[3];
-/** Offset 0x1120 - xHCI High Idle Time LTR override
+/** Offset 0x1108 - xHCI High Idle Time LTR override
Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
**/
UINT32 PchUsbLtrHighIdleTimeOverride;
-/** Offset 0x1124 - xHCI Medium Idle Time LTR override
+/** Offset 0x110C - xHCI Medium Idle Time LTR override
Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
**/
UINT32 PchUsbLtrMediumIdleTimeOverride;
-/** Offset 0x1128 - xHCI Low Idle Time LTR override
+/** Offset 0x1110 - xHCI Low Idle Time LTR override
Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
**/
UINT32 PchUsbLtrLowIdleTimeOverride;
-/** Offset 0x112C - Enable 8254 Static Clock Gating
+/** Offset 0x1114 - Enable 8254 Static Clock Gating
Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
legacy OS using 8254 timer. Also enable this while S0ix is enabled.
@@ -2053,7 +2066,7 @@ typedef struct {
**/
UINT8 Enable8254ClockGating;
-/** Offset 0x112D - Enable 8254 Static Clock Gating On S3
+/** Offset 0x1115 - Enable 8254 Static Clock Gating On S3
This is only applicable when Enable8254ClockGating is disabled. FSP will do the
8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
avoids the SMI requirement for the programming.
@@ -2061,7 +2074,7 @@ typedef struct {
**/
UINT8 Enable8254ClockGatingOnS3;
-/** Offset 0x112E - Enable TCO timer.
+/** Offset 0x1116 - Enable TCO timer.
When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
emulation must be enabled, and WDAT table must not be exposed to the OS.
@@ -2069,105 +2082,105 @@ typedef struct {
**/
UINT8 EnableTcoTimer;
-/** Offset 0x112F - Hybrid Storage Detection and Configuration Mode
+/** Offset 0x1117 - Hybrid Storage Detection and Configuration Mode
Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
Default is 0: Disabled
0: Disabled, 1: Dynamic Configuration
**/
UINT8 HybridStorageMode;
-/** Offset 0x1130 - BgpdtHash[4]
+/** Offset 0x1118 - BgpdtHash[4]
BgpdtHash values
**/
UINT64 BgpdtHash[4];
-/** Offset 0x1150 - BiosGuardAttr
+/** Offset 0x1138 - BiosGuardAttr
BiosGuardAttr default values
**/
UINT32 BiosGuardAttr;
-/** Offset 0x1154 - Reserved
+/** Offset 0x113C - Reserved
**/
- UINT8 Reserved47[4];
+ UINT8 Reserved46[4];
-/** Offset 0x1158 - BiosGuardModulePtr
+/** Offset 0x1140 - BiosGuardModulePtr
BiosGuardModulePtr default values
**/
UINT64 BiosGuardModulePtr;
-/** Offset 0x1160 - SendEcCmd
+/** Offset 0x1148 - SendEcCmd
SendEcCmd function pointer. \n
@code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
**/
UINT64 SendEcCmd;
-/** Offset 0x1168 - EcCmdProvisionEav
+/** Offset 0x1150 - EcCmdProvisionEav
Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
**/
UINT8 EcCmdProvisionEav;
-/** Offset 0x1169 - EcCmdLock
+/** Offset 0x1151 - EcCmdLock
EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
**/
UINT8 EcCmdLock;
-/** Offset 0x116A - Reserved
+/** Offset 0x1152 - Reserved
**/
- UINT8 Reserved48[22];
+ UINT8 Reserved47[22];
-/** Offset 0x1180 - Skip Ssid Programming.
+/** Offset 0x1168 - Skip Ssid Programming.
When set to TRUE, silicon code will not do any SSID programming and platform code
needs to handle that by itself properly.
$EN_DIS
**/
UINT8 SiSkipSsidProgramming;
-/** Offset 0x1181 - Reserved
+/** Offset 0x1169 - Reserved
**/
- UINT8 Reserved49;
+ UINT8 Reserved48;
-/** Offset 0x1182 - Change Default SVID
+/** Offset 0x116A - Change Default SVID
Change the default SVID used in FSP to programming internal devices. This is only
valid when SkipSsidProgramming is FALSE.
**/
UINT16 SiCustomizedSvid;
-/** Offset 0x1184 - Change Default SSID
+/** Offset 0x116C - Change Default SSID
Change the default SSID used in FSP to programming internal devices. This is only
valid when SkipSsidProgramming is FALSE.
**/
UINT16 SiCustomizedSsid;
-/** Offset 0x1186 - Reserved
+/** Offset 0x116E - Reserved
**/
- UINT8 Reserved50[2];
+ UINT8 Reserved49[2];
-/** Offset 0x1188 - SVID SDID table Poniter.
+/** Offset 0x1170 - SVID SDID table Poniter.
The address of the table of SVID SDID to customize each SVID SDID entry. This is
only valid when SkipSsidProgramming is FALSE.
**/
UINT32 SiSsidTablePtr;
-/** Offset 0x118C - Number of ssid table.
+/** Offset 0x1174 - Number of ssid table.
SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
This is only valid when SkipSsidProgramming is FALSE.
**/
UINT16 SiNumberOfSsidTableEntry;
-/** Offset 0x118E - USB2 Port Reset Message Enable
+/** Offset 0x1176 - USB2 Port Reset Message Enable
0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must
be enable for USB2 Port those are paired with CPU XHCI Port
**/
UINT8 PortResetMessageEnable[16];
-/** Offset 0x119E - SATA RST Interrupt Mode
+/** Offset 0x1186 - SATA RST Interrupt Mode
Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
0:Msix, 1:Msi, 2:Legacy
**/
UINT8 SataRstInterrupt;
-/** Offset 0x119F - Enable PS_ON.
+/** Offset 0x1187 - Enable PS_ON.
PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
target that will be required by the California Energy Commission (CEC). When FALSE,
PS_ON is to be disabled.
@@ -2175,114 +2188,114 @@ typedef struct {
**/
UINT8 PsOnEnable;
-/** Offset 0x11A0 - Pmc Cpu C10 Gate Pin Enable
+/** Offset 0x1188 - Pmc Cpu C10 Gate Pin Enable
Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
and VccSTG rails instead of SLP_S0# pin.
$EN_DIS
**/
UINT8 PmcCpuC10GatePinEnable;
-/** Offset 0x11A1 - Pch Dmi Aspm Ctrl
+/** Offset 0x1189 - Pch Dmi Aspm Ctrl
ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
**/
UINT8 PchDmiAspmCtrl;
-/** Offset 0x11A2 - PchDmiCwbEnable
+/** Offset 0x118A - PchDmiCwbEnable
Central Write Buffer feature configurable and enabled by default
$EN_DIS
**/
UINT8 PchDmiCwbEnable;
-/** Offset 0x11A3 - OS IDLE Mode Enable
+/** Offset 0x118B - OS IDLE Mode Enable
Enable/Disable OS Idle Mode
$EN_DIS
**/
UINT8 PmcOsIdleEnable;
-/** Offset 0x11A4 - S0ix Auto-Demotion
+/** Offset 0x118C - S0ix Auto-Demotion
Enable/Disable the Low Power Mode Auto-Demotion Host Control feature.
$EN_DIS
**/
UINT8 PchS0ixAutoDemotion;
-/** Offset 0x11A5 - Latch Events C10 Exit
+/** Offset 0x118D - Latch Events C10 Exit
When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are
captured on C10 exit (instead of C10 entry which is default)
$EN_DIS
**/
UINT8 PchPmLatchEventsC10Exit;
-/** Offset 0x11A6 - Reserved
+/** Offset 0x118E - Reserved
**/
- UINT8 Reserved51[48];
+ UINT8 Reserved50[48];
-/** Offset 0x11D6 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
+/** Offset 0x11BE - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate3UniqTranEnable[10];
-/** Offset 0x11E0 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
+/** Offset 0x11C8 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
= 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate3UniqTran[10];
-/** Offset 0x11EA - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
+/** Offset 0x11D2 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate2UniqTranEnable[10];
-/** Offset 0x11F4 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
+/** Offset 0x11DC - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate2UniqTran[10];
-/** Offset 0x11FE - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
+/** Offset 0x11E6 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate1UniqTranEnable[10];
-/** Offset 0x1208 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
+/** Offset 0x11F0 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate1UniqTran[10];
-/** Offset 0x1212 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
+/** Offset 0x11FA - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate0UniqTranEnable[10];
-/** Offset 0x121C - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
+/** Offset 0x1204 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate0UniqTran[10];
-/** Offset 0x1226 - Skip PAM regsiter lock
+/** Offset 0x120E - Skip PAM regsiter lock
Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
PAM registers will be locked by RC
$EN_DIS
**/
UINT8 SkipPamLock;
-/** Offset 0x1227 - Enable/Disable IGFX RenderStandby
+/** Offset 0x120F - Enable/Disable IGFX RenderStandby
Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
$EN_DIS
**/
UINT8 RenderStandby;
-/** Offset 0x1228 - Reserved
+/** Offset 0x1210 - Reserved
**/
- UINT8 Reserved52;
+ UINT8 Reserved51;
-/** Offset 0x1229 - GT Frequency Limit
+/** Offset 0x1211 - GT Frequency Limit
0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
@@ -2296,51 +2309,51 @@ typedef struct {
**/
UINT8 GtFreqMax;
-/** Offset 0x122A - Disable Turbo GT
+/** Offset 0x1212 - Disable Turbo GT
0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
$EN_DIS
**/
UINT8 DisableTurboGt;
-/** Offset 0x122B - Reserved
+/** Offset 0x1213 - Reserved
**/
- UINT8 Reserved53[2];
+ UINT8 Reserved52[2];
-/** Offset 0x122D - Enable TSN Multi-VC
+/** Offset 0x1215 - Enable TSN Multi-VC
Enable/disable Multi Virtual Channels(VC) in TSN.
$EN_DIS
**/
UINT8 PchTsnMultiVcEnable;
-/** Offset 0x122E - Reserved
+/** Offset 0x1216 - Reserved
**/
- UINT8 Reserved54[2];
+ UINT8 Reserved53[2];
-/** Offset 0x1230 - LogoPixelHeight Address
+/** Offset 0x1218 - LogoPixelHeight Address
Address of LogoPixelHeight
**/
UINT32 LogoPixelHeight;
-/** Offset 0x1234 - LogoPixelWidth Address
+/** Offset 0x121C - LogoPixelWidth Address
Address of LogoPixelWidth
**/
UINT32 LogoPixelWidth;
-/** Offset 0x1238 - Reserved
+/** Offset 0x1220 - Reserved
**/
- UINT8 Reserved55[45];
+ UINT8 Reserved54[45];
-/** Offset 0x1265 - RSR feature
+/** Offset 0x124D - RSR feature
Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
$EN_DIS
**/
UINT8 EnableRsr;
-/** Offset 0x1266 - Reserved
+/** Offset 0x124E - Reserved
**/
- UINT8 Reserved56[4];
+ UINT8 Reserved55[4];
-/** Offset 0x126A - Enable or Disable HWP
+/** Offset 0x1252 - Enable or Disable HWP
Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the
CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; <b>1:
Enable;</b>
@@ -2348,7 +2361,7 @@ typedef struct {
**/
UINT8 Hwp;
-/** Offset 0x126B - Package Long duration turbo mode time
+/** Offset 0x1253 - Package Long duration turbo mode time
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained. Valid values(Unit
@@ -2357,14 +2370,14 @@ typedef struct {
**/
UINT8 PowerLimit1Time;
-/** Offset 0x126C - Short Duration Turbo Mode
+/** Offset 0x1254 - Short Duration Turbo Mode
Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program
the default values for Power Limit 2. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PowerLimit2;
-/** Offset 0x126D - Turbo settings Lock
+/** Offset 0x1255 - Turbo settings Lock
Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT
MSR will be locked and a reset will be required to unlock the register. <b>0: Disable;
</b> 1: Enable
@@ -2372,7 +2385,7 @@ typedef struct {
**/
UINT8 TurboPowerLimitLock;
-/** Offset 0x126E - Package PL3 time window
+/** Offset 0x1256 - Package PL3 time window
Power Limit 3 Time Window value in Milli seconds. Indicates the time window over
which Power Limit 3 value should be maintained. If the value is 0, BIOS leaves
the hardware default value. Valid value: <b>0</b>, 3-8, 10, 12, 14, 16, 20, 24,
@@ -2380,27 +2393,27 @@ typedef struct {
**/
UINT8 PowerLimit3Time;
-/** Offset 0x126F - Package PL3 Duty Cycle
+/** Offset 0x1257 - Package PL3 Duty Cycle
Specify the duty cycle in percentage that the CPU is required to maintain over the
configured time window. Range is 0-100.
**/
UINT8 PowerLimit3DutyCycle;
-/** Offset 0x1270 - Package PL3 Lock
+/** Offset 0x1258 - Package PL3 Lock
Power Limit 3 Lock. When enabled PL3 configurations are locked during OS. When disabled
PL3 configuration can be changed during OS. <b>0: Disable</b> ; 1:Enable
$EN_DIS
**/
UINT8 PowerLimit3Lock;
-/** Offset 0x1271 - Package PL4 Lock
+/** Offset 0x1259 - Package PL4 Lock
Power Limit 4 Lock. When enabled PL4 configurations are locked during OS. When disabled
PL4 configuration can be changed during OS. <b>0: Disable</b> ; 1:Enable
$EN_DIS
**/
UINT8 PowerLimit4Lock;
-/** Offset 0x1272 - TCC Activation Offset
+/** Offset 0x125A - TCC Activation Offset
TCC Activation Offset. Offset from factory set TCC activation temperature at which
the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
@@ -2408,7 +2421,7 @@ typedef struct {
**/
UINT8 TccActivationOffset;
-/** Offset 0x1273 - Tcc Offset Clamp Enable/Disable
+/** Offset 0x125B - Tcc Offset Clamp Enable/Disable
Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
below P1.For SKL Y SKU, the recommended default for this policy is <b>1: Enabled</b>,
For all other SKUs the recommended default are <b>0: Disabled</b>.
@@ -2416,74 +2429,74 @@ typedef struct {
**/
UINT8 TccOffsetClamp;
-/** Offset 0x1274 - Tcc Offset Lock
+/** Offset 0x125C - Tcc Offset Lock
Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
target; <b>0: Disabled</b>; 1: Enabled.
$EN_DIS
**/
UINT8 TccOffsetLock;
-/** Offset 0x1275 - Custom Ratio State Entries
+/** Offset 0x125D - Custom Ratio State Entries
The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
ratio table. Sets the number of custom P-states. At least 2 states must be present
**/
UINT8 NumberOfEntries;
-/** Offset 0x1276 - Custom Short term Power Limit time window
+/** Offset 0x125E - Custom Short term Power Limit time window
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained.
**/
UINT8 Custom1PowerLimit1Time;
-/** Offset 0x1277 - Custom Turbo Activation Ratio
+/** Offset 0x125F - Custom Turbo Activation Ratio
Custom value for Turbo Activation Ratio. Needs to be configured with valid values
from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255
**/
UINT8 Custom1TurboActivationRatio;
-/** Offset 0x1278 - Custom Config Tdp Control
+/** Offset 0x1260 - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom1ConfigTdpControl;
-/** Offset 0x1279 - Custom Short term Power Limit time window
+/** Offset 0x1261 - Custom Short term Power Limit time window
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained.
**/
UINT8 Custom2PowerLimit1Time;
-/** Offset 0x127A - Custom Turbo Activation Ratio
+/** Offset 0x1262 - Custom Turbo Activation Ratio
Custom value for Turbo Activation Ratio. Needs to be configured with valid values
from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255
**/
UINT8 Custom2TurboActivationRatio;
-/** Offset 0x127B - Custom Config Tdp Control
+/** Offset 0x1263 - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom2ConfigTdpControl;
-/** Offset 0x127C - Custom Short term Power Limit time window
+/** Offset 0x1264 - Custom Short term Power Limit time window
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained.
**/
UINT8 Custom3PowerLimit1Time;
-/** Offset 0x127D - Custom Turbo Activation Ratio
+/** Offset 0x1265 - Custom Turbo Activation Ratio
Custom value for Turbo Activation Ratio. Needs to be configured with valid values
from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255
**/
UINT8 Custom3TurboActivationRatio;
-/** Offset 0x127E - Custom Config Tdp Control
+/** Offset 0x1266 - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom3ConfigTdpControl;
-/** Offset 0x127F - ConfigTdp mode settings Lock
+/** Offset 0x1267 - ConfigTdp mode settings Lock
Configurable Processor Base Power (cTDP) Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO
and CONFIG_TDP_CONTROL. Note: When CTDP Lock is enabled Custom ConfigTDP Count
will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0. <b>0:
@@ -2492,7 +2505,7 @@ typedef struct {
**/
UINT8 ConfigTdpLock;
-/** Offset 0x1280 - Load Configurable TDP SSDT
+/** Offset 0x1268 - Load Configurable TDP SSDT
Enables Configurable Processor Base Power (cTDP) control via runtime ACPI BIOS methods.
This "BIOS only" feature does not require EC or driver support. <b>0: Disable</b>;
1: Enable.
@@ -2500,7 +2513,7 @@ typedef struct {
**/
UINT8 ConfigTdpBios;
-/** Offset 0x1281 - PL1 Enable value
+/** Offset 0x1269 - PL1 Enable value
Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it
activates the PL1 value to be used by the processor to limit the average power
of given time window. <b>0: Disable</b>; 1: Enable.
@@ -2508,7 +2521,7 @@ typedef struct {
**/
UINT8 PsysPowerLimit1;
-/** Offset 0x1282 - PL1 timewindow
+/** Offset 0x126A - PL1 timewindow
Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to
128. 0 = default values. Indicates the time window over which Platform Processor
Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to
@@ -2516,7 +2529,7 @@ typedef struct {
**/
UINT8 PsysPowerLimit1Time;
-/** Offset 0x1283 - PL2 Enable Value
+/** Offset 0x126B - PL2 Enable Value
Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS
will program the default values for Platform Power Limit 2. <b>0: Disable</b>;
1: Enable.
@@ -2524,57 +2537,57 @@ typedef struct {
**/
UINT8 PsysPowerLimit2;
-/** Offset 0x1284 - Enable or Disable MLC Streamer Prefetcher
+/** Offset 0x126C - Enable or Disable MLC Streamer Prefetcher
Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MlcStreamerPrefetcher;
-/** Offset 0x1285 - Enable or Disable MLC Spatial Prefetcher
+/** Offset 0x126D - Enable or Disable MLC Spatial Prefetcher
Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 MlcSpatialPrefetcher;
-/** Offset 0x1286 - Enable or Disable Monitor /MWAIT instructions
+/** Offset 0x126E - Enable or Disable Monitor /MWAIT instructions
Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner
should not set in MWAIT Loop. 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MonitorMwaitEnable;
-/** Offset 0x1287 - Enable or Disable initialization of machine check registers
+/** Offset 0x126F - Enable or Disable initialization of machine check registers
Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MachineCheckEnable;
-/** Offset 0x1288 - AP Idle Manner of waiting for SIPI
+/** Offset 0x1270 - AP Idle Manner of waiting for SIPI
AP threads Idle Manner for waiting signal to run. 1: HALT loop; <b>2: MWAIT loop</b>;
3: RUN loop.
1: HALT loop, 2: MWAIT loop, 3: RUN loop
**/
UINT8 ApIdleManner;
-/** Offset 0x1289 - Control on Processor Trace output scheme
+/** Offset 0x1271 - Control on Processor Trace output scheme
Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
0: Single Range Output, 1: ToPA Output
**/
UINT8 ProcessorTraceOutputScheme;
-/** Offset 0x128A - Enable or Disable Processor Trace feature
+/** Offset 0x1272 - Enable or Disable Processor Trace feature
Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ProcessorTraceEnable;
-/** Offset 0x128B - Enable or Disable Intel SpeedStep Technology
+/** Offset 0x1273 - Enable or Disable Intel SpeedStep Technology
Allows more than two frequency ranges to be supported. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Eist;
-/** Offset 0x128C - Enable or Disable Energy Efficient P-state
+/** Offset 0x1274 - Enable or Disable Energy Efficient P-state
Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access
to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 0 indicating no support
for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS
@@ -2584,7 +2597,7 @@ typedef struct {
**/
UINT8 EnergyEfficientPState;
-/** Offset 0x128D - Enable or Disable Energy Efficient Turbo
+/** Offset 0x1275 - Enable or Disable Energy Efficient Turbo
Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically
lower the turbo frequency to increase efficiency. Recommended only to disable in
overclocking situations where turbo frequency must remain constant. Otherwise,
@@ -2593,100 +2606,100 @@ typedef struct {
**/
UINT8 EnergyEfficientTurbo;
-/** Offset 0x128E - Enable or Disable T states
+/** Offset 0x1276 - Enable or Disable T states
Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 TStates;
-/** Offset 0x128F - Enable or Disable Bi-Directional PROCHOT#
+/** Offset 0x1277 - Enable or Disable Bi-Directional PROCHOT#
Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 BiProcHot;
-/** Offset 0x1290 - Enable or Disable PROCHOT# signal being driven externally
+/** Offset 0x1278 - Enable or Disable PROCHOT# signal being driven externally
Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 DisableProcHotOut;
-/** Offset 0x1291 - Enable or Disable PROCHOT# Response
+/** Offset 0x1279 - Enable or Disable PROCHOT# Response
Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ProcHotResponse;
-/** Offset 0x1292 - Enable or Disable VR Thermal Alert
+/** Offset 0x127A - Enable or Disable VR Thermal Alert
Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 DisableVrThermalAlert;
-/** Offset 0x1293 - Enable or Disable Thermal Reporting
+/** Offset 0x127B - Enable or Disable Thermal Reporting
Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 EnableAllThermalFunctions;
-/** Offset 0x1294 - Enable or Disable Thermal Monitor
+/** Offset 0x127C - Enable or Disable Thermal Monitor
Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 ThermalMonitor;
-/** Offset 0x1295 - Enable or Disable CPU power states (C-states)
+/** Offset 0x127D - Enable or Disable CPU power states (C-states)
Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not
100% utilized. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Cx;
-/** Offset 0x1296 - Configure C-State Configuration Lock
+/** Offset 0x127E - Configure C-State Configuration Lock
Configure MSR to CFG Lock bit. 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 PmgCstCfgCtrlLock;
-/** Offset 0x1297 - Enable or Disable Enhanced C-states
+/** Offset 0x127F - Enable or Disable Enhanced C-states
Enable/Disable C1E. When enabled, CPU will switch to minimum speed when all cores
enter C-State. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1e;
-/** Offset 0x1298 - Enable or Disable Package Cstate Demotion
+/** Offset 0x1280 - Enable or Disable Package Cstate Demotion
Enable or Disable Package C-State Demotion. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PkgCStateDemotion;
-/** Offset 0x1299 - Enable or Disable Package Cstate UnDemotion
+/** Offset 0x1281 - Enable or Disable Package Cstate UnDemotion
Enable or Disable Package C-State Un-Demotion. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PkgCStateUnDemotion;
-/** Offset 0x129A - Enable or Disable CState-Pre wake
+/** Offset 0x1282 - Enable or Disable CState-Pre wake
Disable - to disable the Cstate Pre-Wake. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 CStatePreWake;
-/** Offset 0x129B - Enable or Disable TimedMwait Support.
+/** Offset 0x1283 - Enable or Disable TimedMwait Support.
Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 TimedMwait;
-/** Offset 0x129C - Enable or Disable IO to MWAIT redirection
+/** Offset 0x1284 - Enable or Disable IO to MWAIT redirection
When set, will map IO_read instructions sent to IO registers PMG_IO_BASE_ADDRBASE+offset
to MWAIT(offset). <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 CstCfgCtrIoMwaitRedirection;
-/** Offset 0x129D - Set the Max Pkg Cstate
+/** Offset 0x1285 - Set the Max Pkg Cstate
Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value.
Auto: Initializes to deepest available Package C State Limit. Valid values 0 -
C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 -
@@ -2694,74 +2707,74 @@ typedef struct {
**/
UINT8 PkgCStateLimit;
-/** Offset 0x129E - TimeUnit for C-State Latency Control0
+/** Offset 0x1286 - TimeUnit for C-State Latency Control0
TimeUnit for C-State Latency Control0, Valid values 0 - 1ns, 1 - 32ns, <b>2 - 1024ns</b>,
3 - 32768ns, 4 - 1048576ns, 5 - 33554432ns
**/
UINT8 CstateLatencyControl0TimeUnit;
-/** Offset 0x129F - TimeUnit for C-State Latency Control1
+/** Offset 0x1287 - TimeUnit for C-State Latency Control1
TimeUnit for C-State Latency Control1, Valid values 0 - 1ns, 1 - 32ns, <b>2 - 1024ns</b>,
3 - 32768ns, 4 - 1048576ns, 5 - 33554432ns
**/
UINT8 CstateLatencyControl1TimeUnit;
-/** Offset 0x12A0 - TimeUnit for C-State Latency Control2
+/** Offset 0x1288 - TimeUnit for C-State Latency Control2
TimeUnit for C-State Latency Control2, Valid values 0 - 1ns, 1 - 32ns, <b>2 - 1024ns</b>,
3 - 32768ns, 4 - 1048576ns, 5 - 33554432ns
**/
UINT8 CstateLatencyControl2TimeUnit;
-/** Offset 0x12A1 - TimeUnit for C-State Latency Control3
+/** Offset 0x1289 - TimeUnit for C-State Latency Control3
TimeUnit for C-State Latency Control3, Valid values 0 - 1ns, 1 - 32ns, <b>2 - 1024ns</b>,
3 - 32768ns, 4 - 1048576ns, 5 - 33554432ns
**/
UINT8 CstateLatencyControl3TimeUnit;
-/** Offset 0x12A2 - TimeUnit for C-State Latency Control4
+/** Offset 0x128A - TimeUnit for C-State Latency Control4
TimeUnit for C-State Latency Control4, Valid values 0 - 1ns, 1 - 32ns, <b>2 - 1024ns</b>,
3 - 32768ns, 4 - 1048576ns, 5 - 33554432ns
**/
UINT8 CstateLatencyControl4TimeUnit;
-/** Offset 0x12A3 - TimeUnit for C-State Latency Control5
+/** Offset 0x128B - TimeUnit for C-State Latency Control5
TimeUnit for C-State Latency Control5, Valid values 0 - 1ns, 1 - 32ns, <b>2 - 1024ns</b>,
3 - 32768ns, 4 - 1048576ns, 5 - 33554432ns
**/
UINT8 CstateLatencyControl5TimeUnit;
-/** Offset 0x12A4 - Interrupt Redirection Mode Select
+/** Offset 0x128C - Interrupt Redirection Mode Select
Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1:
Round robin; 2: Hash vector; 7: No change.
**/
UINT8 PpmIrmSetting;
-/** Offset 0x12A5 - Lock prochot configuration
+/** Offset 0x128D - Lock prochot configuration
Lock prochot configuration Enable/Disable; 0: Disable;<b> 1: Enable</b>
$EN_DIS
**/
UINT8 ProcHotLock;
-/** Offset 0x12A6 - Configuration for boot TDP selection
+/** Offset 0x128E - Configuration for boot TDP selection
Configurable Processor Base Power (cTDP) Mode as Nominal/Level1/Level2/Deactivate
TDP selection. Deactivate option will set MSR to Nominal and MMIO to Zero. <b>0:
TDP Nominal</b>; 1: TDP Down; 2: TDP Up;0xFF : Deactivate
**/
UINT8 ConfigTdpLevel;
-/** Offset 0x12A7 - Max P-State Ratio
+/** Offset 0x128F - Max P-State Ratio
Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F
**/
UINT8 MaxRatio;
-/** Offset 0x12A8 - P-state ratios for custom P-state table
+/** Offset 0x1290 - P-state ratios for custom P-state table
P-state ratios for custom P-state table. NumberOfEntries has valid range between
0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
are configurable. Valid Range of each entry is 0 to 0x7F
**/
UINT8 StateRatio[40];
-/** Offset 0x12D0 - P-state ratios for max 16 version of custom P-state table
+/** Offset 0x12B8 - P-state ratios for max 16 version of custom P-state table
P-state ratios for max 16 version of custom P-state table. This table is used for
OS versions limited to a max of 16 P-States. If the first entry of this table is
0, or if Number of Entries is 16 or less, then this table will be ignored, and
@@ -2770,7 +2783,7 @@ typedef struct {
**/
UINT8 StateRatioMax16[16];
-/** Offset 0x12E0 - Package Long duration turbo mode power limit
+/** Offset 0x12C8 - Package Long duration turbo mode power limit
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -2780,7 +2793,7 @@ typedef struct {
**/
UINT32 PowerLimit1;
-/** Offset 0x12E4 - Package Short duration turbo mode power limit
+/** Offset 0x12CC - Package Short duration turbo mode power limit
Power Limit 2 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. If the value is 0, BIOS will program this value as 1.25*Processor
Base Power (TDP). Processor applies control policies such that the package power
@@ -2789,7 +2802,7 @@ typedef struct {
**/
UINT32 PowerLimit2Power;
-/** Offset 0x12E8 - Package PL3 power limit
+/** Offset 0x12D0 - Package PL3 power limit
Power Limit 3 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. XE SKU: Any value can be programmed. Overclocking SKU: Value
must be between Max and Min Power Limits. Other SKUs: This value must be between
@@ -2799,24 +2812,24 @@ typedef struct {
**/
UINT32 PowerLimit3;
-/** Offset 0x12EC - Package PL4 power limit
+/** Offset 0x12D4 - Package PL4 power limit
Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. If the value is 0, BIOS leaves default value. Units are based
on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767.
**/
UINT32 PowerLimit4;
-/** Offset 0x12F0 - Reserved
+/** Offset 0x12D8 - Reserved
**/
- UINT8 Reserved57[4];
+ UINT8 Reserved56[4];
-/** Offset 0x12F4 - Tcc Offset Time Window for RATL
+/** Offset 0x12DC - Tcc Offset Time Window for RATL
Configure Power Limit 4 Boost in Watts. Valid Range 0 to 1023 in step size of 1
Watt. The value 0 means disable.
**/
UINT32 TccOffsetTimeWindowForRatl;
-/** Offset 0x12F8 - Short term Power Limit value for custom cTDP level 1
+/** Offset 0x12E0 - Short term Power Limit value for custom cTDP level 1
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -2825,7 +2838,7 @@ typedef struct {
**/
UINT32 Custom1PowerLimit1;
-/** Offset 0x12FC - Long term Power Limit value for custom cTDP level 1
+/** Offset 0x12E4 - Long term Power Limit value for custom cTDP level 1
Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Processor applies control policies
such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -2833,7 +2846,7 @@ typedef struct {
**/
UINT32 Custom1PowerLimit2;
-/** Offset 0x1300 - Short term Power Limit value for custom cTDP level 2
+/** Offset 0x12E8 - Short term Power Limit value for custom cTDP level 2
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -2842,7 +2855,7 @@ typedef struct {
**/
UINT32 Custom2PowerLimit1;
-/** Offset 0x1304 - Long term Power Limit value for custom cTDP level 2
+/** Offset 0x12EC - Long term Power Limit value for custom cTDP level 2
Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Processor applies control policies
such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -2850,7 +2863,7 @@ typedef struct {
**/
UINT32 Custom2PowerLimit2;
-/** Offset 0x1308 - Short term Power Limit value for custom cTDP level 3
+/** Offset 0x12F0 - Short term Power Limit value for custom cTDP level 3
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -2859,7 +2872,7 @@ typedef struct {
**/
UINT32 Custom3PowerLimit1;
-/** Offset 0x130C - Long term Power Limit value for custom cTDP level 3
+/** Offset 0x12F4 - Long term Power Limit value for custom cTDP level 3
Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Processor applies control policies
such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -2867,7 +2880,7 @@ typedef struct {
**/
UINT32 Custom3PowerLimit2;
-/** Offset 0x1310 - Platform PL1 power
+/** Offset 0x12F8 - Platform PL1 power
Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W
when programming. Value set 120 = 15W. Any value can be programmed between Max
and Min Power Limits. This setting will act as the new PL1 value for the Package
@@ -2876,7 +2889,7 @@ typedef struct {
**/
UINT32 PsysPowerLimit1Power;
-/** Offset 0x1314 - Platform PL2 power
+/** Offset 0x12FC - Platform PL2 power
Platform Power Limit 2 Power in Milli Watts. BIOS will round to the nearest 1/8W
when programming. Value set 120 = 15W. Any value can be programmed between Max
and Min Power Limits. This setting will act as the new PL2 value for the Package
@@ -2885,7 +2898,11 @@ typedef struct {
**/
UINT32 PsysPowerLimit2Power;
-/** Offset 0x1318 - Race To Halt
+/** Offset 0x1300 - Reserved
+**/
+ UINT8 Reserved57;
+
+/** Offset 0x1301 - Race To Halt
Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
in order to enter pkg C-State faster to reduce overall power. 0: Disable; <b>1:
Enable</b>
@@ -2893,66 +2910,66 @@ typedef struct {
**/
UINT8 RaceToHalt;
-/** Offset 0x1319 - Reserved
+/** Offset 0x1302 - Reserved
**/
UINT8 Reserved58;
-/** Offset 0x131A - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
+/** Offset 0x1303 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 HwpInterruptControl;
-/** Offset 0x131B - Reserved
+/** Offset 0x1304 - Reserved
**/
UINT8 Reserved59[4];
-/** Offset 0x131F - Intel Turbo Boost Max Technology 3.0
+/** Offset 0x1308 - Intel Turbo Boost Max Technology 3.0
Enable/Disable Intel(R) Turbo Boost Max Technology 3.0 support. Disabling will report
the maximum ratio of the slowest core in _CPC object. 0: Disabled; <b>1: Enabled</b>
$EN_DIS
**/
UINT8 EnableItbm;
-/** Offset 0x1320 - Enable or Disable C1 Cstate Demotion
+/** Offset 0x1309 - Enable or Disable C1 Cstate Demotion
Enable or Disable C1 Cstate Auto Demotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1StateAutoDemotion;
-/** Offset 0x1321 - Enable or Disable C1 Cstate UnDemotion
+/** Offset 0x130A - Enable or Disable C1 Cstate UnDemotion
Enable or Disable C1 Cstate Un-Demotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1StateUnDemotion;
-/** Offset 0x1322 - Minimum Ring ratio limit override
+/** Offset 0x130B - Minimum Ring ratio limit override
Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
ratio limit
**/
UINT8 MinRingRatioLimit;
-/** Offset 0x1323 - Maximum Ring ratio limit override
+/** Offset 0x130C - Maximum Ring ratio limit override
Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
ratio limit
**/
UINT8 MaxRingRatioLimit;
-/** Offset 0x1324 - Enable or Disable Per Core P State OS control
+/** Offset 0x130D - Enable or Disable Per Core P State OS control
Enable/Disable Per Core P state OS control mode. When set, the highest core request
is used for all other core requests. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 EnablePerCorePState;
-/** Offset 0x1325 - Enable or Disable HwP Autonomous Per Core P State OS control
+/** Offset 0x130E - Enable or Disable HwP Autonomous Per Core P State OS control
Disable Autonomous PCPS Autonomous will request the same value for all cores all
the time. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 EnableHwpAutoPerCorePstate;
-/** Offset 0x1326 - Enable or Disable HwP Autonomous EPP Grouping
+/** Offset 0x130F - Enable or Disable HwP Autonomous EPP Grouping
Enable EPP grouping Autonomous will request the same values for all cores with same
EPP. Disable EPP grouping autonomous will not necessarily request same values for
all cores with same EPP. 0: Disable; <b>1: Enable</b>
@@ -2960,7 +2977,7 @@ typedef struct {
**/
UINT8 EnableHwpAutoEppGrouping;
-/** Offset 0x1327 - Enable Configurable TDP
+/** Offset 0x1310 - Enable Configurable TDP
Applies Configurable Processor Base Power (cTDP) initialization settings based on
non-cTDP or cTDP. Default is 1: Applies to cTDP; if 0 then applies non-cTDP and
BIOS will bypass cTDP initialzation flow
@@ -2968,42 +2985,42 @@ typedef struct {
**/
UINT8 ApplyConfigTdp;
-/** Offset 0x1328 - Reserved
+/** Offset 0x1311 - Reserved
**/
UINT8 Reserved60;
-/** Offset 0x1329 - Dual Tau Boost
+/** Offset 0x1312 - Dual Tau Boost
Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W
sku. When DPTF is enabled this feature is ignored. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 DualTauBoost;
-/** Offset 0x132A - Reserved
+/** Offset 0x1313 - Reserved
**/
UINT8 Reserved61[32];
-/** Offset 0x134A - End of Post message
+/** Offset 0x1333 - End of Post message
Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE
0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
**/
UINT8 EndOfPostMessage;
-/** Offset 0x134B - D0I3 Setting for HECI Disable
+/** Offset 0x1334 - D0I3 Setting for HECI Disable
Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
HECI devices
$EN_DIS
**/
UINT8 DisableD0I3SettingForHeci;
-/** Offset 0x134C - Mctp Broadcast Cycle
+/** Offset 0x1335 - Mctp Broadcast Cycle
Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 MctpBroadcastCycle;
-/** Offset 0x134D - ME Unconfig on RTC clear
+/** Offset 0x1336 - ME Unconfig on RTC clear
0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
2: Cmos is clear, status unkonwn. 3: Reserved
0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
@@ -3011,151 +3028,155 @@ typedef struct {
**/
UINT8 MeUnconfigOnRtcClear;
-/** Offset 0x134E - Enforce Enhanced Debug Mode
+/** Offset 0x1337 - Enforce Enhanced Debug Mode
Determine if ME should enter Enhanced Debug Mode. <b>0: disable</b>, 1: enable
$EN_DIS
**/
UINT8 EnforceEDebugMode;
-/** Offset 0x134F - Reserved
+/** Offset 0x1338 - Reserved
**/
UINT8 Reserved62[17];
-/** Offset 0x1360 - Enable LOCKDOWN SMI
+/** Offset 0x1349 - Enable LOCKDOWN SMI
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
$EN_DIS
**/
UINT8 PchLockDownGlobalSmi;
-/** Offset 0x1361 - Enable LOCKDOWN BIOS Interface
+/** Offset 0x134A - Enable LOCKDOWN BIOS Interface
Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
$EN_DIS
**/
UINT8 PchLockDownBiosInterface;
-/** Offset 0x1362 - Unlock all GPIO pads
+/** Offset 0x134B - Unlock all GPIO pads
Force all GPIO pads to be unlocked for debug purpose.
$EN_DIS
**/
UINT8 PchUnlockGpioPads;
-/** Offset 0x1363 - PCH Unlock SideBand access
+/** Offset 0x134C - PCH Unlock SideBand access
The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
$EN_DIS
**/
UINT8 PchSbAccessUnlock;
-/** Offset 0x1364 - PCIE RP Ltr Max Snoop Latency
+/** Offset 0x134D - Reserved
+**/
+ UINT8 Reserved63;
+
+/** Offset 0x134E - PCIE RP Ltr Max Snoop Latency
Latency Tolerance Reporting, Max Snoop Latency.
**/
UINT16 PcieRpLtrMaxSnoopLatency[24];
-/** Offset 0x1394 - PCIE RP Ltr Max No Snoop Latency
+/** Offset 0x137E - PCIE RP Ltr Max No Snoop Latency
Latency Tolerance Reporting, Max Non-Snoop Latency.
**/
UINT16 PcieRpLtrMaxNoSnoopLatency[24];
-/** Offset 0x13C4 - PCIE RP Snoop Latency Override Mode
+/** Offset 0x13AE - PCIE RP Snoop Latency Override Mode
Latency Tolerance Reporting, Snoop Latency Override Mode.
**/
UINT8 PcieRpSnoopLatencyOverrideMode[28];
-/** Offset 0x13E0 - PCIE RP Snoop Latency Override Multiplier
+/** Offset 0x13CA - PCIE RP Snoop Latency Override Multiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
**/
UINT8 PcieRpSnoopLatencyOverrideMultiplier[28];
-/** Offset 0x13FC - PCIE RP Snoop Latency Override Value
+/** Offset 0x13E6 - PCIE RP Snoop Latency Override Value
Latency Tolerance Reporting, Snoop Latency Override Value.
**/
UINT16 PcieRpSnoopLatencyOverrideValue[24];
-/** Offset 0x142C - PCIE RP Non Snoop Latency Override Mode
+/** Offset 0x1416 - PCIE RP Non Snoop Latency Override Mode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
**/
UINT8 PcieRpNonSnoopLatencyOverrideMode[28];
-/** Offset 0x1448 - PCIE RP Non Snoop Latency Override Multiplier
+/** Offset 0x1432 - PCIE RP Non Snoop Latency Override Multiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
**/
UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[28];
-/** Offset 0x1464 - PCIE RP Non Snoop Latency Override Value
+/** Offset 0x144E - PCIE RP Non Snoop Latency Override Value
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
**/
UINT16 PcieRpNonSnoopLatencyOverrideValue[24];
-/** Offset 0x1494 - PCIE RP Slot Power Limit Scale
+/** Offset 0x147E - PCIE RP Slot Power Limit Scale
Specifies scale used for slot power limit value. Leave as 0 to set to default.
**/
UINT8 PcieRpSlotPowerLimitScale[28];
-/** Offset 0x14B0 - PCIE RP Slot Power Limit Value
+/** Offset 0x149A - PCIE RP Slot Power Limit Value
Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
**/
UINT16 PcieRpSlotPowerLimitValue[24];
-/** Offset 0x14E0 - PCIE RP Enable Port8xh Decode
+/** Offset 0x14CA - PCIE RP Enable Port8xh Decode
This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
1: Enable.
$EN_DIS
**/
UINT8 PcieEnablePort8xhDecode;
-/** Offset 0x14E1 - PCIE Port8xh Decode Port Index
+/** Offset 0x14CB - PCIE Port8xh Decode Port Index
The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
**/
UINT8 PchPciePort8xhDecodePortIndex;
-/** Offset 0x14E2 - PCH Energy Reporting
+/** Offset 0x14CC - PCH Energy Reporting
Disable/Enable PCH to CPU energy report feature.
$EN_DIS
**/
UINT8 PchPmDisableEnergyReport;
-/** Offset 0x14E3 - PCH Sata Test Mode
+/** Offset 0x14CD - PCH Sata Test Mode
Allow entrance to the PCH SATA test modes.
$EN_DIS
**/
UINT8 SataTestMode;
-/** Offset 0x14E4 - PCH USB OverCurrent mapping lock enable
+/** Offset 0x14CE - PCH USB OverCurrent mapping lock enable
If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
$EN_DIS
**/
UINT8 PchXhciOcLock;
-/** Offset 0x14E5 - Low Power Mode Enable/Disable config mask
+/** Offset 0x14CF - Low Power Mode Enable/Disable config mask
Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds
to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4.
**/
UINT8 PmcLpmS0ixSubStateEnableMask;
-/** Offset 0x14E6 - Reserved
+/** Offset 0x14D0 - Reserved
**/
- UINT8 Reserved63;
+ UINT8 Reserved64[2];
-/** Offset 0x14E7 - PMC C10 dynamic threshold dajustment enable
+/** Offset 0x14D2 - PMC C10 dynamic threshold dajustment enable
Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
$EN_DIS
**/
UINT8 PmcC10DynamicThresholdAdjustment;
-/** Offset 0x14E8 - Reserved
+/** Offset 0x14D3 - Reserved
**/
- UINT8 Reserved64[32];
+ UINT8 Reserved65[33];
-/** Offset 0x1508 - FspEventHandler
+/** Offset 0x14F4 - FspEventHandler
<b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
**/
UINT32 FspEventHandler;
-/** Offset 0x150C - Reserved
+/** Offset 0x14F8 - Reserved
**/
- UINT8 Reserved65[20];
+ UINT8 Reserved66[16];
} FSP_S_CONFIG;
/** Fsp S UPD Configuration
@@ -3174,11 +3195,11 @@ typedef struct {
**/
FSP_S_CONFIG FspsConfig;
-/** Offset 0x1520
+/** Offset 0x1508
**/
- UINT8 UnusedUpdSpace39[6];
+ UINT8 UnusedUpdSpace41[6];
-/** Offset 0x1526
+/** Offset 0x150E
**/
UINT16 UpdTerminator;
} FSPS_UPD;