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authorRex-BC Chen <rex-bc.chen@mediatek.com>2022-07-28 18:46:30 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-08-03 16:40:20 +0000
commit245fe4bd2933f43b9203f0c602bf59d3bf98ce21 (patch)
tree4ce6ae9f0d13fdc2dd034d3c5256ad6a11ea4bb9
parent07c91d55db461b74320a2e04c035f2c5533a1622 (diff)
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soc/mediatek: Move common definitions to dramc_soc_common.h
Some definitions are the same in dramc_soc.h for MT8192, MT8195 and MT8186, so we move them to dramc_soc_common.h TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3095333e62abf98de1f2d27033baeeba7a4cad79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66276 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/mediatek/common/include/soc/dramc_soc_common.h22
-rw-r--r--src/soc/mediatek/mt8186/include/soc/dramc_soc.h18
-rw-r--r--src/soc/mediatek/mt8192/include/soc/dramc_soc.h18
-rw-r--r--src/soc/mediatek/mt8195/include/soc/dramc_soc.h18
4 files changed, 28 insertions, 48 deletions
diff --git a/src/soc/mediatek/common/include/soc/dramc_soc_common.h b/src/soc/mediatek/common/include/soc/dramc_soc_common.h
new file mode 100644
index 00000000000..8898709f4b3
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/dramc_soc_common.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_DRAMC_SOC_COMMON_H__
+#define __SOC_MEDIATEK_DRAMC_SOC_COMMON_H__
+
+/*
+ * Internal CBT mode enum
+ * 1. Calibration flow uses vGet_Dram_CBT_Mode to
+ * differentiate between mixed vs non-mixed LP4
+ * 2. Declared as dram_cbt_mode[RANK_MAX] internally to
+ * store each rank's CBT mode type
+ */
+typedef enum {
+ CBT_NORMAL_MODE = 0,
+ CBT_BYTE_MODE1,
+} DRAM_CBT_MODE_T;
+
+#define DQS_NUMBER_LP4 2
+#define DQS_BIT_NUMBER 8
+#define DQ_DATA_WIDTH_LP4 16
+
+#endif /* __SOC_MEDIATEK_DRAMC_SOC_COMMON_H__ */
diff --git a/src/soc/mediatek/mt8186/include/soc/dramc_soc.h b/src/soc/mediatek/mt8186/include/soc/dramc_soc.h
index 5602e144cbc..ba768de119d 100644
--- a/src/soc/mediatek/mt8186/include/soc/dramc_soc.h
+++ b/src/soc/mediatek/mt8186/include/soc/dramc_soc.h
@@ -3,6 +3,8 @@
#ifndef __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__
#define __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__
+#include <soc/dramc_soc_common.h>
+
typedef enum {
CHANNEL_A = 0,
CHANNEL_B,
@@ -35,22 +37,6 @@ typedef enum {
DRAM_DFS_SHUFFLE_MAX,
} DRAM_DFS_SHUFFLE_TYPE_T;
-/*
- * Internal CBT mode enum
- * 1. Calibration flow uses vGet_Dram_CBT_Mode to
- * differentiate between mixed vs non-mixed LP4
- * 2. Declared as dram_cbt_mode[RANK_MAX] internally to
- * store each rank's CBT mode type
- */
-typedef enum {
- CBT_NORMAL_MODE = 0,
- CBT_BYTE_MODE1,
-} DRAM_CBT_MODE_T;
-
#define DRAM_DFS_SHU_MAX DRAM_DFS_SHUFFLE_MAX
-#define DQS_NUMBER_LP4 2
-#define DQS_BIT_NUMBER 8
-#define DQ_DATA_WIDTH_LP4 16
-
#endif /* __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__ */
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_soc.h b/src/soc/mediatek/mt8192/include/soc/dramc_soc.h
index 8710563160b..49aef400b30 100644
--- a/src/soc/mediatek/mt8192/include/soc/dramc_soc.h
+++ b/src/soc/mediatek/mt8192/include/soc/dramc_soc.h
@@ -3,6 +3,8 @@
#ifndef __SOC_MEDIATEK_DRAMC_SOC_H__
#define __SOC_MEDIATEK_DRAMC_SOC_H__
+#include <soc/dramc_soc_common.h>
+
typedef enum {
CHANNEL_A = 0,
CHANNEL_B,
@@ -26,22 +28,6 @@ typedef enum {
DRAM_DFS_SHUFFLE_MAX
} DRAM_DFS_SHUFFLE_TYPE_T; // DRAM SHUFFLE RG type
-/*
- * Internal CBT mode enum
- * 1. Calibration flow uses vGet_Dram_CBT_Mode to
- * differentiate between mixed vs non-mixed LP4
- * 2. Declared as dram_cbt_mode[RANK_MAX] internally to
- * store each rank's CBT mode type
- */
-typedef enum {
- CBT_NORMAL_MODE = 0,
- CBT_BYTE_MODE1
-} DRAM_CBT_MODE_T;
-
#define DRAM_DFS_SHU_MAX DRAM_DFS_SHUFFLE_MAX
-#define DQS_NUMBER_LP4 2
-#define DQS_BIT_NUMBER 8
-#define DQ_DATA_WIDTH_LP4 16
-
#endif /* __SOC_MEDIATEK_DRAMC_SOC_H__ */
diff --git a/src/soc/mediatek/mt8195/include/soc/dramc_soc.h b/src/soc/mediatek/mt8195/include/soc/dramc_soc.h
index 60402979928..cc5f54e63b5 100644
--- a/src/soc/mediatek/mt8195/include/soc/dramc_soc.h
+++ b/src/soc/mediatek/mt8195/include/soc/dramc_soc.h
@@ -3,6 +3,8 @@
#ifndef __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__
#define __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__
+#include <soc/dramc_soc_common.h>
+
typedef enum {
CHANNEL_A = 0,
CHANNEL_B,
@@ -29,22 +31,6 @@ typedef enum {
DRAM_DFS_SHUFFLE_MAX,
} DRAM_DFS_SHUFFLE_TYPE_T;
-/*
- * Internal CBT mode enum
- * 1. Calibration flow uses vGet_Dram_CBT_Mode to
- * differentiate between mixed vs non-mixed LP4
- * 2. Declared as dram_cbt_mode[RANK_MAX] internally to
- * store each rank's CBT mode type
- */
-typedef enum {
- CBT_NORMAL_MODE = 0,
- CBT_BYTE_MODE1,
-} DRAM_CBT_MODE_T;
-
#define DRAM_DFS_SHU_MAX DRAM_DFS_SHUFFLE_MAX
-#define DQS_NUMBER_LP4 2
-#define DQS_BIT_NUMBER 8
-#define DQ_DATA_WIDTH_LP4 16
-
#endif /* __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__ */