soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` config

List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.

Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a81fd58df468e2711108a3243bf116e02986316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

11 files changed, 6 insertions, 34 deletions

diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 1fa7d2fa5fbe..5e5a5863dd4a 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -87,9 +87,6 @@ chip soc/intel/tigerlake
 	register "pmc_gpe0_dw1" = "GPP_D"
 	register "pmc_gpe0_dw2" = "GPP_E"
 
-	# Enable heci communication
-	register "HeciEnabled" = "1"
-
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
 
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index d01fdd635251..2c9a548ae0ff 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -8,9 +8,6 @@ chip soc/intel/tigerlake
 	register "pmc_gpe0_dw1" = "GPP_C"
 	register "pmc_gpe0_dw2" = "GPP_D"
 
-	# Enable heci1 communication
-	register "HeciEnabled" = "1"
-
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
 
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index c0adcc3f50cc..d19747a5c0ab 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -8,9 +8,6 @@ chip soc/intel/tigerlake
 	register "pmc_gpe0_dw1" = "GPP_C"
 	register "pmc_gpe0_dw2" = "GPP_D"
 
-	# Enable heci1 communication
-	register "HeciEnabled" = "1"
-
 	# FSP configuration
 	register "SaGv" = "SaGv_Disabled"
 
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
index fb559d284e03..66b8e86eb789 100644
--- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
@@ -18,7 +18,6 @@ chip soc/intel/tigerlake
 	register "CnviBtCore"			= "true"
 	register "CnviBtAudioOffload"		= "1"
 	register "enable_c6dram"		= "1"
-	register "HeciEnabled"			= "1"
 	register "SaGv"				= "SaGv_Enabled"
 	register "TcssD3ColdDisable"		= "1"
 
diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb
index ae91bdd00550..21f8141c5f92 100644
--- a/src/mainboard/system76/darp7/devicetree.cb
+++ b/src/mainboard/system76/darp7/devicetree.cb
@@ -242,9 +242,7 @@ chip soc/intel/tigerlake
 			# TODO: USB-PD?
 			register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
 		end
-		device ref heci1 on
-			register "HeciEnabled" = "1"
-		end
+		device ref heci1 on end
 		device ref uart2 on
 			# Debug console
 			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb
index 716afd4d0a22..8bc74e34e151 100644
--- a/src/mainboard/system76/galp5/devicetree.cb
+++ b/src/mainboard/system76/galp5/devicetree.cb
@@ -253,9 +253,7 @@ chip soc/intel/tigerlake
 			# TODO: Pantone ROM?
 			register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
 		end
-		device ref heci1 on
-			register "HeciEnabled" = "1"
-		end
+		device ref heci1 on end
 		device ref uart2 on
 			# Debug console
 			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
diff --git a/src/mainboard/system76/gaze16/devicetree.cb b/src/mainboard/system76/gaze16/devicetree.cb
index 8b43202860a0..a92f0449753c 100644
--- a/src/mainboard/system76/gaze16/devicetree.cb
+++ b/src/mainboard/system76/gaze16/devicetree.cb
@@ -123,9 +123,7 @@ chip soc/intel/tigerlake
 				device i2c 15 on end
 			end
 		end
-		device ref heci1 on
-			register "HeciEnabled" = "1"
-		end
+		device ref heci1 on end
 		device ref uart2 on
 			# Debug console
 			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb
index f097baceceeb..fc6c3b1774eb 100644
--- a/src/mainboard/system76/lemp10/devicetree.cb
+++ b/src/mainboard/system76/lemp10/devicetree.cb
@@ -223,9 +223,7 @@ chip soc/intel/tigerlake
 			# TODO: USB-PD?
 			register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
 		end
-		device ref heci1 on
-			register "HeciEnabled" = "1"
-		end
+		device ref heci1 on end
 		device ref uart2 on
 			# Debug console
 			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb
index b85818d892de..d3cf5de9c9ce 100644
--- a/src/mainboard/system76/oryp8/devicetree.cb
+++ b/src/mainboard/system76/oryp8/devicetree.cb
@@ -158,9 +158,7 @@ chip soc/intel/tigerlake
 				device i2c 2c on end
 			end
 		end
-		device ref heci1 on
-			register "HeciEnabled" = "1"
-		end
+		device ref heci1 on end
 		device ref uart2 on
 			# Debug console
 			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 59651d58b39d..538fe91fd9c0 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -276,10 +276,6 @@ struct soc_intel_tigerlake_config {
 	/* Gfx related */
 	uint8_t SkipExtGfxScan;
 
-	/* HeciEnabled decides the state of Heci1 at end of boot
-	 * Setting to 0 (default) disables Heci1 and hides the device from OS */
-	uint8_t HeciEnabled;
-
 	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
 	uint8_t eist_enable;
 
diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c
index 6280fb28bddc..8e343c3c754d 100644
--- a/src/soc/intel/tigerlake/smihandler.c
+++ b/src/soc/intel/tigerlake/smihandler.c
@@ -16,11 +16,7 @@
  */
 void smihandler_soc_at_finalize(void)
 {
-	const struct soc_intel_tigerlake_config *config;
-
-	config = config_of_soc();
-
-	if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
+	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
 		heci_disable();
 }