diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-10 15:06:33 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-10-13 11:07:00 +0000 |
| commit | b9c9cd75e71edf2fb9b34c451e7ad74a5200de1d (patch) | |
| tree | b5b3a4327f21a40011605347c2a3694bac6e6efa | |
| parent | b33d8ce5c7cb71117a7a65a0775c5a16c7bc4517 (diff) | |
| download | coreboot-b9c9cd75e71edf2fb9b34c451e7ad74a5200de1d.tar.gz coreboot-b9c9cd75e71edf2fb9b34c451e7ad74a5200de1d.tar.bz2 coreboot-b9c9cd75e71edf2fb9b34c451e7ad74a5200de1d.zip | |
sb/intel/ibexpeak: Move some early PCH init after console init
Some of the initialization isn't necessary before console INIT is
done.
EHCI debug still works fine on the Lenovo Thinkpad X201.
Change-Id: I0c33efd98844f7188e0258cf9f90049d45145e7c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35949
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/northbridge/intel/nehalem/romstage.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/early_pch.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 1 |
3 files changed, 9 insertions, 2 deletions
diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c index c465a9936545..54766de0e702 100644 --- a/src/northbridge/intel/nehalem/romstage.c +++ b/src/northbridge/intel/nehalem/romstage.c @@ -45,11 +45,13 @@ void mainboard_romstage_entry(void) /* TODO, make this configurable */ nehalem_early_initialization(NEHALEM_MOBILE); - early_pch_init(); + pch_pre_console_init(); /* Initialize console device(s) */ console_init(); + early_pch_init(); + /* Read PM1_CNT, DON'T CLEAR IT or raminit will fail! */ reg32 = inl(DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 2707eb2cb81c..ccd8f7443157 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -80,10 +80,14 @@ static void pch_default_disable(void) RCBA32(FD2) = 1; } -void early_pch_init(void) +void pch_pre_console_init(void) { early_lpc_init(); mainboard_lpc_init(); +} + +void early_pch_init(void) +{ early_gpio_init(); /* TODO, make this configurable */ pch_setup_cir(NEHALEM_MOBILE); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index b9632371aca0..1449ee914d63 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -62,6 +62,7 @@ int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); #endif +void pch_pre_console_init(void); void early_pch_init(void); void early_thermal_init(void); |