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| author | Saurabh Mishra <mishra.saurabh@intel.com> | 2022-07-28 10:24:23 +0530 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-08-07 19:39:43 +0000 |
| commit | debb8085c6869caaa83cf80d35e035cb9e97ddce (patch) | |
| tree | fae12c498866dd50db97a9fc5ce526e0ec9ed867 | |
| parent | df864709a5d185602f9cb4ab42689dba02ecbc35 (diff) | |
| download | coreboot-debb8085c6869caaa83cf80d35e035cb9e97ddce.tar.gz coreboot-debb8085c6869caaa83cf80d35e035cb9e97ddce.tar.bz2 coreboot-debb8085c6869caaa83cf80d35e035cb9e97ddce.zip | |
vc/intel/fsp: Update ADL N FSP headers from v3222.03 to v3267.01
Update generated FSP headers for Alder Lake N from v3222.03 to v3267.01.
Changes include:
- Add UPD Lp5BankMode
- Update UPD Offset in FspmUpd.h
BUG=b:240373012
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp"and boot Nissa.
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb522e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66222
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h index a687eb0ad1c2..c33aebf6deff 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h @@ -3201,7 +3201,17 @@ typedef struct { /** Offset 0x0AA8 - Reserved **/ - UINT8 Reserved45[144]; + UINT8 Reserved45[130]; + +/** Offset 0x0B2A - LP5 Bank Mode + LP5 Bank Mode. 0: Auto, 1: 8 Bank Mode, 2: 16 Bank Mode, 3: BG Mode, default is 0 + 0:Auto, 1:8 Bank Mode, 2:16 Bank Mode, 3:BG Mode +**/ + UINT8 Lp5BankMode; + +/** Offset 0x0B2B - Reserved +**/ + UINT8 Reserved46[13]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -3222,7 +3232,7 @@ typedef struct { /** Offset 0x0B38 **/ - UINT8 UnusedUpdSpace34[6]; + UINT8 UnusedUpdSpace33[6]; /** Offset 0x0B3E **/ |