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authorFrans Hendriks <fhendriks@eltan.com>2022-08-03 09:43:17 +0200
committerMartin L Roth <gaumless@gmail.com>2022-08-07 19:30:43 +0000
commitfd1a53f5c19d288bb56a326bb32fc07e93bbd2bf (patch)
treef5d1d8247b525dbeffee608c79418f0472ac836f
parent1750877ffd05074054efb8a143296074dd306d22 (diff)
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soc/intel/tigerlake: Expose In-Band ECC config to mainboard
Support for feature "In-Band ECC" not available for Tiger Lake Similar to Elkhart Lake, Tiger Lake also provides this feature. Ported from Elkhart Lake (CB:55668) Bug = N/A TEST = Build and boot Siemens AS-TGL1 Change-Id: Ie54d5f6a9747fad0105d0f8bf725be611bb8cf60 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
-rw-r--r--src/soc/intel/tigerlake/chip.h21
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params.c16
2 files changed, 37 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 746cfa22257..6e15d504869 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -25,6 +25,24 @@
#define MAX_HD_AUDIO_SNDW_LINKS 4
#define MAX_HD_AUDIO_SSP_LINKS 6
+/* Define config parameters for In-Band ECC (IBECC). */
+#define MAX_IBECC_REGIONS 8
+
+enum ibecc_mode {
+ IBECC_PER_REGION,
+ IBECC_NONE,
+ IBECC_ALL
+};
+
+struct ibecc_config {
+ bool enable;
+ bool parity_en;
+ enum ibecc_mode mode;
+ bool region_enable[MAX_IBECC_REGIONS];
+ uint16_t region_base[MAX_IBECC_REGIONS];
+ uint16_t region_mask[MAX_IBECC_REGIONS];
+};
+
/* The first two are for TGL-U */
enum soc_intel_tigerlake_power_limits {
POWER_LIMITS_U_2_CORE,
@@ -152,6 +170,9 @@ struct soc_intel_tigerlake_config {
/* TCC activation offset */
uint32_t tcc_offset;
+ /* In-Band ECC (IBECC) configuration */
+ struct ibecc_config ibecc;
+
/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
* When enabled memory will be training at two different frequencies.
* 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index e07d2392643..a9cb2ece4e8 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -212,6 +212,22 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
/* crashLog config */
m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT);
m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice;
+
+ /* In-Band ECC configuration */
+ if (config->ibecc.enable) {
+ m_cfg->Ibecc = !!config->ibecc.enable;
+ m_cfg->IbeccParity = !!config->ibecc.parity_en;
+ m_cfg->IbeccOperationMode = config->ibecc.mode;
+ if (m_cfg->IbeccOperationMode == IBECC_PER_REGION) {
+ FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionEnable,
+ config->ibecc.region_enable);
+ FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionBase,
+ config->ibecc.region_base);
+ FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionMask,
+ config->ibecc.region_mask);
+ }
+ }
+
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)