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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-11-05 08:32:19 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-11 10:24:50 +0000 |
| commit | 1b95501fad0b94098a1e6c5be637efaf113dcb88 (patch) | |
| tree | 3c29ba076b5f1c147c9b9ca98015b1f622e60998 /Documentation/releases | |
| parent | 12440ce63e3f96b32311f4ebde4ef0861dbcec02 (diff) | |
| download | coreboot-1b95501fad0b94098a1e6c5be637efaf113dcb88.tar.gz coreboot-1b95501fad0b94098a1e6c5be637efaf113dcb88.tar.bz2 coreboot-1b95501fad0b94098a1e6c5be637efaf113dcb88.zip | |
Documentation: Add some significant 4.11 release notes
Change-Id: Ia881cfa9382d0b2fa2652696b912030af942b68a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'Documentation/releases')
| -rw-r--r-- | Documentation/releases/coreboot-4.11-relnotes.md | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index 7dd99a352293..38299c13a6d1 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -40,3 +40,22 @@ removed soon after release. Significant refactoring has bee done to achieve some consistency across platforms and to reduce code duplication. + +### Added VBOOT support to the following platforms: +* intel/gm45 +* intel/nehalem + +### Moved the following platforms to C_ENVIRONMENT_BOOTBLOCK: +* intel/gm45 +* intel/nehalem +* intel/braswell + +### Other +* Did cleanups around TSC timer +* Improved automatic VR configuration on SKL/KBL +* Filled additional fields in SMBIOS type 4 +* Removed magic value replay from Intel Nehalem/ibexpeak code base +* Added OpenSBI on RISCV platforms +* Did more preparations for Intel TXT support +* Did more preparations for x86_64 stage support +* Added SSDT generator for arbitrary SuperIO chips based on devicetree.cb |