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| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2021-03-31 22:27:20 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-04-16 14:37:03 +0000 |
| commit | 369405090fc73e60f2e26f7bc1c5a8acc8305a5e (patch) | |
| tree | b5741d15dd857cbcf3097b6505bfc1faa3edab92 /Documentation | |
| parent | 67ffcfa176966542269c32deb342cda22d38516a (diff) | |
| download | coreboot-369405090fc73e60f2e26f7bc1c5a8acc8305a5e.tar.gz coreboot-369405090fc73e60f2e26f7bc1c5a8acc8305a5e.tar.bz2 coreboot-369405090fc73e60f2e26f7bc1c5a8acc8305a5e.zip | |
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2117_00
The headers added are generated as per FSP v2117_00.
Previous FSP version was v2081_02.
Changes Include:
- Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h
- Remove FivrFaults and FivrEfficiency Upds from FspmUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h
BUG=b:184129128
BRANCH=None
TEST=Build and boot ADLRVP
Change-Id: I068552084b1ef3e5c4fba7a46240d116c92c7b5b
Cq-Depend: TBD
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions