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| author | Martin Roth <gaumless@gmail.com> | 2022-10-22 20:34:41 -0600 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2022-10-30 01:48:45 +0000 |
| commit | 14cedd97a5790fe6182771630d91bfa375abf867 (patch) | |
| tree | 82bd5ee217f83ff5b04caf57ef10e311d823ab7d /MAINTAINERS | |
| parent | b10578a404a82df1c3d49190ae6b4568eb4ac8f1 (diff) | |
| download | coreboot-14cedd97a5790fe6182771630d91bfa375abf867.tar.gz coreboot-14cedd97a5790fe6182771630d91bfa375abf867.tar.bz2 coreboot-14cedd97a5790fe6182771630d91bfa375abf867.zip | |
MAINTAINERS: Make Misc Fixes
- X86 architecture is maintained, so mark it as such.
- Legacy AMD chips are supported for odd fixes.
- Remove maintainers whose emails are bouncing.
- Remove maintainers who don't have +2 rights in gerrit.
- According to the instructions, we should use S: Orphan, not Orphaned.
- Update incorrect email addresses.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib6d47a8c34482c81ff96dbeec760852cba01dabc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index e109c42e1635..61d43e076306 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -665,6 +665,7 @@ F: src/mainboard/sifive/ F: util/riscv/ X86 ARCHITECTURE +S: MAINTAINED F: src/arch/x86/ F: src/cpu/x86/ F: src/drivers/pc80/ @@ -740,6 +741,7 @@ F: src/northbridge/intel/x4x/ AMD SUPPORT L: amd_coreboot_org_changes@googlegroups.com +S: Odd Fixes F: src/vendorcode/amd/ F: src/cpu/amd/ F: src/northbridge/amd/ @@ -757,9 +759,7 @@ F: src/drivers/intel/ F: src/include/cpu/intel/ INTEL FSP 1.1 -M: Lee Leahy <leroy.p.leahy@intel.com> M: Huang Jin <huang.jin@intel.com> -M: York Yang <york.yang@intel.com> S: Supported F: src/drivers/intel/fsp1_1/ @@ -877,7 +877,6 @@ F: src/soc/intel/tigerlake/ INTEL Xeon Sacalable Processor Family M: Jonathan Zhang <jonzhang@fb.com> -M: Reddy Chagam <anjaneya.chagam@intel.com> M: Johnny Lin <Johnny_Lin@wiwynn.com> M: Tim Chu <Tim.Chu@quantatw.com> M: Arthur Heymans <arthur@aheymans.xyz> @@ -899,7 +898,7 @@ F: src/soc/mediatek/mt8192/ F: src/vendorcode/mediatek/mt8192/ ORPHANED ARM SOCS -S: Orphaned +S: Orphan F: src/cpu/armltd/ F: src/soc/ti/ F: src/soc/qualcomm/ @@ -1153,7 +1152,7 @@ MISSING: SPI CODE OF CONDUCT M: Stefan Reinauer <stefan.reinauer@coreboot.org> -M: Ronald Minnich <rminnich@coreboot.org> +M: Ronald Minnich <rminnich@gmail.com> M: Martin Roth <martin@coreboot.org> S: Maintained F: Documentation/community/code_of_conduct.md |