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| author | Shuo Liu <shuo.liu@intel.com> | 2024-03-11 22:03:23 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-05-16 21:05:28 +0000 |
| commit | 43a54184b0f8bdde9cff361a9aded25715bec454 (patch) | |
| tree | 6eab6bebbf249022e5b47b23c53d3f5acedea35d /configs/builder | |
| parent | 921ddba69ee1513de162c2ea65018124de4c95f1 (diff) | |
| download | coreboot-43a54184b0f8bdde9cff361a9aded25715bec454.tar.gz coreboot-43a54184b0f8bdde9cff361a9aded25715bec454.tar.bz2 coreboot-43a54184b0f8bdde9cff361a9aded25715bec454.zip | |
mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
Beechnut City CRB is the 2 socket reference board for 6th Gen Xeon-SP
SP SoCs (Granite Rapids SP and Sierra Forest SP).
This patch initially sets the code set up as a compilation target with
GNR N-1 FSP, and with basic feature supports (Integrated IO Controller
(IIO) configuration, BMC, UART, HPET).
TEST=Build on intel/beechnutcity CRB
Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'configs/builder')
| -rw-r--r-- | configs/builder/config.intel.crb.bnc | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/configs/builder/config.intel.crb.bnc b/configs/builder/config.intel.crb.bnc new file mode 100644 index 000000000000..843940c2e737 --- /dev/null +++ b/configs/builder/config.intel.crb.bnc @@ -0,0 +1,50 @@ +# Type this in coreboot root directory to get a working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.bnc + +# +# [RO] Board Configurations +# +CONFIG_VENDOR_INTEL=y +CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB=y + +CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y +CONFIG_CONFIGURABLE_RAMSTAGE=y + +CONFIG_NO_GFX_INIT=y + +CONFIG_HAVE_IFD_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_LINUX=y + +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_CONSOLE_SERIAL_115200=y + +# +# [RW] IFWI Ingredients +# +CONFIG_IFD_BIN_PATH="site-local/beechnutcity/descriptor.bin" +CONFIG_CPU_UCODE_BINARIES="site-local/beechnutcity/ucode.mcb" +CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd" +CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd" +CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd" +CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/" + +CONFIG_PAYLOAD_FILE="site-local/beechnutcity/linuxboot_bzImage" +CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200" + +# +# [RW] Debug Settings +# +CONFIG_CONSOLE_POST=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y + +CONFIG_VERIFY_HOBS=y +CONFIG_DISPLAY_MTRRS=y + +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y + +CONFIG_HAVE_DEBUG_GPIO=y +CONFIG_DEBUG_GPIO=y |