Make C7/CN700 boot to memtest86, and pass that test. Booting is very slow, ~15min to get to a memtest

payload.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1077 f3766cd6-281f-0410-b1cd-43a5c92072e9

12 files changed, 248 insertions, 93 deletions

diff --git a/northbridge/via/cn700/Makefile b/northbridge/via/cn700/Makefile
index d34202204835..0317b59b8411 100644
--- a/northbridge/via/cn700/Makefile
+++ b/northbridge/via/cn700/Makefile
@@ -20,9 +20,12 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_VIA_CN700),y)
 
-STAGE2_CHIPSET_SRC += 	$(src)/northbridge/via/cn700/stage2.c \
+STAGE2_CHIPSET_SRC += 	$(src)/northbridge/via/cn700/apic.c \
 			$(src)/northbridge/via/cn700/agp.c \
+			$(src)/northbridge/via/cn700/memctrl.c \
 			$(src)/northbridge/via/cn700/pci.c \
-			$(src)/northbridge/via/cn700/vga.c
+			$(src)/northbridge/via/cn700/pci_domain.c \
+			$(src)/northbridge/via/cn700/vga.c \
+			$(src)/arch/x86/via/c7.c
 
 endif
diff --git a/northbridge/via/cn700/agp.c b/northbridge/via/cn700/agp.c
index 3d7a3c848de1..f06bfc2abf21 100644
--- a/northbridge/via/cn700/agp.c
+++ b/northbridge/via/cn700/agp.c
@@ -108,7 +108,8 @@ struct device_operations cn700_agp = {
 	.constructor			= default_device_constructor,
 	.phase3_scan			= 0,
 	.phase4_read_resources		= pci_dev_read_resources,
-	//.phase4_set_resources		= pci_set_resources,
-	//.phase5_enable_resources	= pci_dev_enable_resources,
+	.phase4_set_resources		= pci_set_resources,
+	.phase5_enable_resources	= pci_dev_enable_resources,
 	.phase6_init			= agp_init,
+	.ops_pci_bus			= &pci_cf8_conf1,
 };
diff --git a/northbridge/via/cn700/stage2.h b/northbridge/via/cn700/agp.dts
index 3fafa1f1c95e..f43b0ba2e1f2 100644
--- a/northbridge/via/cn700/stage2.h
+++ b/northbridge/via/cn700/agp.dts
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+ * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef NORTHBRIDGE_VIA_CN700_STAGE2_H
-#define NORTHBRIDGE_VIA_CN700_STAGE2_H
-
-extern unsigned int cn700_scan_root_bus(device_t root, unsigned int max);
-
-#endif
+{
+	device_operations = "cn700_agp";
+};
diff --git a/northbridge/via/cn700/apic.c b/northbridge/via/cn700/apic.c
new file mode 100644
index 000000000000..2ebfaf2b9fba
--- /dev/null
+++ b/northbridge/via/cn700/apic.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <arch/x86/cpu.h>
+
+
+static void cpu_bus_init(struct device *dev)
+{
+#warning "cpu_bus_init() empty, what should it do?"
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
+	printk(BIOS_SPEW, ">> Exiting northbridge.c: %s\n", __FUNCTION__);
+}
+
+static void cpu_bus_noop(struct device *dev)
+{
+}
+
+/** Operations for when the northbridge is running an APIC cluster. */
+struct device_operations cn700_north_apic = {
+	.id = {.type = DEVICE_ID_APIC_CLUSTER,
+		{.apic_cluster = {.vendor = PCI_VENDOR_ID_VIA,
+				       .device = PCI_DEVICE_ID_VIA_CN700_AGP}}},
+	.constructor			= default_device_constructor,
+	.phase3_scan			= 0,
+	.phase4_read_resources		= cpu_bus_noop,
+	.phase4_set_resources		= cpu_bus_noop,
+	.phase5_enable_resources	= cpu_bus_noop,
+	.phase6_init			= cpu_bus_init,
+};
diff --git a/northbridge/via/cn700/apic.dts b/northbridge/via/cn700/apic.dts
new file mode 100644
index 000000000000..899d78c4ac27
--- /dev/null
+++ b/northbridge/via/cn700/apic.dts
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "cn700_north_apic";
+};
diff --git a/northbridge/via/cn700/memctrl.c b/northbridge/via/cn700/memctrl.c
index 553d378e145d..99ccea0c1e81 100644
--- a/northbridge/via/cn700/memctrl.c
+++ b/northbridge/via/cn700/memctrl.c
@@ -33,7 +33,7 @@ static void memctrl_init(struct device *dev)
 	u8 ranks, pagec, paged, pagee, pagef, shadowreg;
 
 	/* Set up the VGA framebuffer size. */
-	reg16 = (log2(CONFIG_CN700_VIDEO_MB_32) << 12) | (1 << 15);
+	reg16 = (log2f(CONFIG_CN700_VIDEO_MB_32) << 12) | (1 << 15);
 	pci_write_config16(dev, 0xa0, reg16);
 
 	/* Set up VGA timers. */
@@ -57,6 +57,7 @@ static void memctrl_init(struct device *dev)
 	/* TODO: This doesn't belong here. At the very least make it a dts
 	 * option */
 
+#if 0	/* Handled in stage1 */
 	/* Shadow RAM */
 	pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30;
 	/* PAGE C, D, E are all read write enable */
@@ -68,26 +69,25 @@ static void memctrl_init(struct device *dev)
 	shadowreg |= pagef;
 	pci_write_config8(dev, 0x83, shadowreg);
 	/* vlink mirror */
-	vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
-				    PCI_DEVICE_ID_VIA_CN700_VLINK, 0);
-	if (vlink_dev) {
-		pci_write_config8(vlink_dev, 0x61, pagec);
-		pci_write_config8(vlink_dev, 0x62, paged);
-		pci_write_config8(vlink_dev, 0x64, pagee);
-
-		shadowreg = pci_read_config8(vlink_dev, 0x63);
-		shadowreg |= pagef;
-		pci_write_config8(vlink_dev, 0x63, shadowreg);
-	}
+	vlink_dev = dev_find_slot(0, PCI_BDF(0, 7, 0))
+	pci_write_config8(vlink_dev, 0x61, pagec);
+	pci_write_config8(vlink_dev, 0x62, paged);
+	pci_write_config8(vlink_dev, 0x64, pagee);
+	shadowreg = pci_read_config8(vlink_dev, 0x63);
+	shadowreg |= pagef;
+	pci_write_config8(vlink_dev, 0x63, shadowreg);
+#endif
 }
 
-static const struct device_operations memctrl_operations = {
-	.read_resources = cn700_noop,
-	.init           = memctrl_init,
-};
-
-static const struct pci_driver memctrl_driver __pci_driver = {
-	.ops    = &memctrl_operations,
-	.vendor = PCI_VENDOR_ID_VIA,
-	.device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL,
+struct device_operations cn700_memctrl = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_VIA,
+				.device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL}}},
+	.constructor			= default_device_constructor,
+	//.phase3_scan			= scan_static_bus,
+	.phase4_read_resources		= pci_dev_read_resources,
+	.phase4_set_resources		= pci_set_resources,
+	.phase5_enable_resources	= pci_dev_enable_resources,
+	.phase6_init			= memctrl_init,
+	.ops_pci		 	= &pci_dev_ops_pci,
 };
diff --git a/northbridge/via/cn700/memctrl.dts b/northbridge/via/cn700/memctrl.dts
new file mode 100644
index 000000000000..5c64f540bfb1
--- /dev/null
+++ b/northbridge/via/cn700/memctrl.dts
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "cn700_memctrl";
+};
diff --git a/northbridge/via/cn700/pci.c b/northbridge/via/cn700/pci.c
index 3f8f2cefc8c7..89a47630911c 100644
--- a/northbridge/via/cn700/pci.c
+++ b/northbridge/via/cn700/pci.c
@@ -54,8 +54,9 @@ struct device_operations cn700_pci_bridge = {
 				.device = PCI_DEVICE_ID_VIA_CN700_BRIDGE}}},
 	.constructor			= default_device_constructor,
 	.phase3_scan			= pci_scan_bridge,
-	.phase4_read_resources		= pci_dev_read_resources,
-	//.phase4_set_resources		= pci_set_resources,
-	//.phase5_enable_resources	= pci_dev_enable_resources,
+	.phase4_read_resources		= NULL,
+	.phase4_set_resources		= pci_set_resources,
+	.phase5_enable_resources	= pci_bus_enable_resources,
 	.phase6_init			= pci_bridge_init,
+	.ops_pci_bus			= &pci_cf8_conf1,
 };
diff --git a/northbridge/via/cn700/pci.dts b/northbridge/via/cn700/pci.dts
new file mode 100644
index 000000000000..3a2386d076b8
--- /dev/null
+++ b/northbridge/via/cn700/pci.dts
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "cn700_pci_bridge";
+};
diff --git a/northbridge/via/cn700/stage2.c b/northbridge/via/cn700/pci_domain.c
index faba9ef74c86..78b3f5ee2a9b 100644
--- a/northbridge/via/cn700/stage2.c
+++ b/northbridge/via/cn700/pci_domain.c
@@ -63,60 +63,57 @@ static u32 find_pci_tolm(struct bus *bus)
 
 static const u8 ramregs[4] = {0x43, 0x42, 0x41, 0x40};
 
-static void pci_domain_set_resources(struct device *dev)
+static void cn700_pci_domain_set_resources(struct device *dev)
 {
 	struct device *mc_dev;
-	u32 pci_tolm;
+	u32 pci_tolm, tomk, tolmk;
+	u8 rambits;
+	int i, idx;
 
 	printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n");
 
+#if 0
+	if(!(pci_read_config8(dev, 0xe0) & (1 << 7)) || !(pci_read_config8(dev, 0x4f) & 1))
+	{
+		printk(BIOS_DEBUG, "Northbridge multifunction disabled, re-enabling");
+		rambits = pci_read_config8(dev, 0x4f);
+		rambits |= 1;
+		pci_write_config8(dev, 0x4f, rambits);
+	} else
+		printk(BIOS_DEBUG, "Northrbidge multifunction enabled");
+#endif
+
 	pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev_find_pci_device(PCI_VENDOR_ID_VIA,
-				 PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
-
-	if (mc_dev) {
-		u32 tomk, tolmk;
-		u8 rambits;
-		int i, idx;
-
-		/*
-		 * Once the register value is not zero, the RAM size is
-		 * this register's value multiply 64 * 1024 * 1024.
-		 */
-		for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
-			rambits = pci_read_config8(mc_dev, ramregs[i]);
-			if (rambits != 0)
-				break;
-		}
-
-		tomk = rambits * 64 * 1024;
-		printk(BIOS_SPEW, "tomk is 0x%x\n", tomk);
-		/* Compute the Top Of Low Memory (TOLM), in Kb. */
-		tolmk = pci_tolm >> 10;
-		if (tolmk >= tomk) {
-			/* The PCI hole does does not overlap the memory. */
-			tolmk = tomk;
-		}
-		/* Report the memory regions. */
-		idx = 10;
-		/* TODO: Hole needed? */
-		ram_resource(dev, idx++, 0, 640);	/* First 640k */
-		/* Leave a hole for VGA, 0xa0000 - 0xc0000 */
-		ram_resource(dev, idx++, 768,
-			     (tolmk - 768 - CONFIG_CN700_VIDEO_MB_32 * 1024));
+				PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
+	
+
+	/*
+	 * Once the register value is not zero, the RAM size is
+	 * this register's value multiply 64 * 1024 * 1024.
+	 */
+	for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
+		rambits = pci_read_config8(mc_dev, ramregs[i]);
+		if (rambits != 0)
+			break;
 	}
-	phase4_assign_resources(&dev->link[0]);
-}
-
-static void cpu_bus_init(struct device *dev)
-{
-#warning "cpu_bus_init() empty, what should it do?"
-	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
-	printk(BIOS_SPEW, ">> Exiting northbridge.c: %s\n", __FUNCTION__);
-}
 
-static void cpu_bus_noop(struct device *dev)
-{
+	tomk = rambits * 64 * 1024;
+	printk(BIOS_SPEW, "tomk is 0x%x\n", tomk);
+	/* Compute the Top Of Low Memory (TOLM), in Kb. */
+	tolmk = pci_tolm >> 10;
+	if (tolmk >= tomk) {
+		/* The PCI hole does does not overlap the memory. */
+		tolmk = tomk;
+	}
+	/* Report the memory regions. */
+	idx = 10;
+	/* TODO: Hole needed? */
+	ram_resource(dev, idx++, 0, 640);	/* First 640k */
+	/* Leave a hole for VGA, 0xa0000 - 0xc0000 */
+	ram_resource(dev, idx++, 768,
+		     (tolmk - 768 - (CONFIG_CN700_VIDEO_MB * 1024)));
+	phase4_assign_resources(&dev->link[0]);
 }
 
 /** Operations for when the northbridge is running a PCI domain. */
@@ -127,20 +124,10 @@ struct device_operations cn700_north_domain = {
 	.constructor			= default_device_constructor,
 	.phase3_scan			= pci_domain_scan_bus,
 	.phase4_read_resources		= pci_domain_read_resources,
-	.phase4_set_resources		= pci_domain_set_resources,
+	.phase4_set_resources		= cn700_pci_domain_set_resources,
 	.phase5_enable_resources	= enable_childrens_resources,
 	.phase6_init			= 0,
+	.ops_pci_bus			= &pci_cf8_conf1,
 };
 
-/** Operations for when the northbridge is running an APIC cluster. */
-struct device_operations cn700_north_apic = {
-	.id = {.type = DEVICE_ID_APIC_CLUSTER,
-		{.apic_cluster = {.vendor = PCI_VENDOR_ID_VIA,
-				       .device = PCI_DEVICE_ID_VIA_CN700_AGP}}},
-	.constructor			= default_device_constructor,
-	.phase3_scan			= 0,
-	.phase4_read_resources		= cpu_bus_noop,
-	.phase4_set_resources		= cpu_bus_noop,
-	.phase5_enable_resources	= cpu_bus_noop,
-	.phase6_init			= cpu_bus_init,
-};
+
diff --git a/northbridge/via/cn700/pci_domain.dts b/northbridge/via/cn700/pci_domain.dts
new file mode 100644
index 000000000000..0854967baa78
--- /dev/null
+++ b/northbridge/via/cn700/pci_domain.dts
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "cn700_north_domain";
+};
diff --git a/northbridge/via/cn700/vga.dts b/northbridge/via/cn700/vga.dts
new file mode 100644
index 000000000000..7e951db6829f
--- /dev/null
+++ b/northbridge/via/cn700/vga.dts
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "cn700_vga";
+};