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| author | Ronald G. Minnich <rminnich@gmail.com> | 2008-11-14 16:21:21 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2008-11-14 16:21:21 +0000 |
| commit | dd5e033e5fef3361ea204db11998ce62f6b557dd (patch) | |
| tree | 651bf704637ff56f1b1b1747754439519892bfaa /northbridge | |
| parent | 981c3652a11d84bebc161712fb799f4817f23554 (diff) | |
| download | coreboot-dd5e033e5fef3361ea204db11998ce62f6b557dd.tar.gz coreboot-dd5e033e5fef3361ea204db11998ce62f6b557dd.tar.bz2 coreboot-dd5e033e5fef3361ea204db11998ce62f6b557dd.zip | |
Get rid of un-needed functions in initram.c
Comment out not-yet-supplied initialize_cpus.
Fix missing ; in smbus.c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1025 f3766cd6-281f-0410-b1cd-43a5c92072e9
Diffstat (limited to 'northbridge')
| -rw-r--r-- | northbridge/intel/i945/northbridge.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/northbridge/intel/i945/northbridge.c b/northbridge/intel/i945/northbridge.c index cddbf6e42474..15917416ca9a 100644 --- a/northbridge/intel/i945/northbridge.c +++ b/northbridge/intel/i945/northbridge.c @@ -209,7 +209,8 @@ static void mc_read_resources(struct device * dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08llx.\n", + + printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", (u64) resource->base, (u64) (resource->base + resource->size)); } @@ -250,10 +251,12 @@ struct device_operations i945_mc_ops = { .ops_pci = &intel_pci_ops, }; - +#warning need to write initialize_cpus static void cpu_bus_init(struct device * dev) { + /* what to do here? initialize_cpus(&dev->link[0]); + */ } static void cpu_bus_noop(struct device * dev) |