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| author | Logan Carlson <logancarlson@google.com> | 2017-05-30 15:31:10 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-02 18:30:53 +0200 |
| commit | c058d1c0f8c04a0fca778f70701d7f903754b0b6 (patch) | |
| tree | e2b54717a77ccb2b14a9314a75be3741850ebdf5 /src/arch/arm/include | |
| parent | f848ed091e49ab076b5d4dccc7ccff429ecea445 (diff) | |
| download | coreboot-c058d1c0f8c04a0fca778f70701d7f903754b0b6.tar.gz coreboot-c058d1c0f8c04a0fca778f70701d7f903754b0b6.tar.bz2 coreboot-c058d1c0f8c04a0fca778f70701d7f903754b0b6.zip | |
arch/arm: Correct checkpatch errors
Correct whitespace issues in arch/arm and arch/arm64.
Enclose complex values in parenthesis.
Change-Id: I74b68f485adff1e6f0fa433e51e12b59ccea654b
Signed-off-by: Logan Carlson <logancarlson@google.com>
Reviewed-on: https://review.coreboot.org/19989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/arch/arm/include')
| -rw-r--r-- | src/arch/arm/include/armv4/arch/smp/spinlock.h | 10 | ||||
| -rw-r--r-- | src/arch/arm/include/armv7.h | 6 | ||||
| -rw-r--r-- | src/arch/arm/include/smp/spinlock.h | 4 |
3 files changed, 10 insertions, 10 deletions
diff --git a/src/arch/arm/include/armv4/arch/smp/spinlock.h b/src/arch/arm/include/armv4/arch/smp/spinlock.h index 6c5f6e88d928..e49dc4440a44 100644 --- a/src/arch/arm/include/armv4/arch/smp/spinlock.h +++ b/src/arch/arm/include/armv4/arch/smp/spinlock.h @@ -15,12 +15,12 @@ #define _ARCH_SMP_SPINLOCK_H #define DECLARE_SPIN_LOCK(x) -#define barrier() do {} while(0) +#define barrier() do {} while (0) #define spin_is_locked(lock) 0 -#define spin_unlock_wait(lock) do {} while(0) -#define spin_lock(lock) do {} while(0) -#define spin_unlock(lock) do {} while(0) -#define cpu_relax() do {} while(0) +#define spin_unlock_wait(lock) do {} while (0) +#define spin_lock(lock) do {} while (0) +#define spin_unlock(lock) do {} while (0) +#define cpu_relax() do {} while (0) #include <smp/node.h> #define boot_cpu() 1 diff --git a/src/arch/arm/include/armv7.h b/src/arch/arm/include/armv7.h index 6622a6f9d4e1..bec7fd70334e 100644 --- a/src/arch/arm/include/armv7.h +++ b/src/arch/arm/include/armv7.h @@ -54,8 +54,8 @@ * However, we use the CP15 based instructions because we use * -march=armv5 in U-Boot */ -#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) -#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) -#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) +#define CP15ISB (asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))) +#define CP15DSB (asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))) +#define CP15DMB (asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))) #endif /* ARMV7_H */ diff --git a/src/arch/arm/include/smp/spinlock.h b/src/arch/arm/include/smp/spinlock.h index a8f9c77c7360..f98900a66b3d 100644 --- a/src/arch/arm/include/smp/spinlock.h +++ b/src/arch/arm/include/smp/spinlock.h @@ -29,9 +29,9 @@ typedef struct { #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } #define DECLARE_SPIN_LOCK(x) static spinlock_t x = SPIN_LOCK_UNLOCKED; -#define barrier() __asm__ __volatile__("": : :"memory") +#define barrier() (__asm__ __volatile__("" : : : "memory")) #define spin_is_locked(x) (*(volatile char *)(&(x)->lock) != 0) -#define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x)) +#define spin_unlock_wait(x) do { barrier(); } while (spin_is_locked(x)) static inline __attribute__((always_inline)) void spin_lock(spinlock_t *lock) { |