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author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-07-13 09:39:15 +0200 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-07-13 21:04:56 +0200 |
commit | 6cb3a59fd5e754c3627b79db21c5bcc284bfd721 (patch) | |
tree | e83db5b11ee4a29d496dcf2798d024b6b8455ab7 /src/arch/x86/cpu_common.c | |
parent | 9693885ad88d21ead7bd9ebc32f3e4901841b18b (diff) | |
download | coreboot-962bf7a29a3a5bc538d0ddb44d6ba78c8125805b.tar.gz coreboot-962bf7a29a3a5bc538d0ddb44d6ba78c8125805b.tar.bz2 coreboot-962bf7a29a3a5bc538d0ddb44d6ba78c8125805b.zip |
It never made sense to have bootblock_* in init, but
pirq_routing.c in boot, and some ld scripts on the main
level while others live in subdirectories.
This patch flattens the directory hierarchy and makes
x86 more similar to the other architectures.
Change-Id: I4056038fe7813e4d3d3042c441e7ab6076a36384
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10901
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/x86/cpu_common.c')
-rw-r--r-- | src/arch/x86/cpu_common.c | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c new file mode 100644 index 000000000000..af0ab2ae9866 --- /dev/null +++ b/src/arch/x86/cpu_common.c @@ -0,0 +1,65 @@ +#include <console/console.h> +#include <cpu/cpu.h> +#include <arch/io.h> +#include <string.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <arch/cpu.h> +#include <device/path.h> +#include <device/device.h> +#include <smp/spinlock.h> + +#ifndef __x86_64__ +/* Standard macro to see if a specific flag is changeable */ +static inline int flag_is_changeable_p(uint32_t flag) +{ + uint32_t f1, f2; + + asm( + "pushfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "movl %0,%1\n\t" + "xorl %2,%0\n\t" + "pushl %0\n\t" + "popfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "popfl\n\t" + : "=&r" (f1), "=&r" (f2) + : "ir" (flag)); + return ((f1^f2) & flag) != 0; +} + +/* Probe for the CPUID instruction */ +int cpu_have_cpuid(void) +{ + return flag_is_changeable_p(X86_EFLAGS_ID); +} + +#else + +int cpu_have_cpuid(void) +{ + return 1; +} +#endif + +int cpu_cpuid_extended_level(void) +{ + return cpuid_eax(0x80000000); +} + +int cpu_phys_address_size(void) +{ + if (!(cpu_have_cpuid())) + return 32; + + if (cpu_cpuid_extended_level() >= 0x80000008) + return cpuid_eax(0x80000008) & 0xff; + + if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) + return 36; + return 32; +} |