src/arch: Improve code formatting

Change-Id: Ic1ca6c2e1cd06800d7eb2d00ac0b328987d022ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16434
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker

7 files changed, 119 insertions, 119 deletions

diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index b1c1aac0c039..6c085e920e0f 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -280,53 +280,53 @@ void mmu_init(void)
 	for (; (pte_t *)_ettb_subtables - table > 0; table += SUBTABLE_PTES)
 		table[0] = ATTR_UNUSED;
 
-        if (CONFIG_ARM_LPAE) {
-                pte_t *const pgd_buff = (pte_t*)(_ttb + 16*KiB);
-                pte_t *pmd = ttb_buff;
-                int i;
+	if (CONFIG_ARM_LPAE) {
+		pte_t *const pgd_buff = (pte_t*)(_ttb + 16*KiB);
+		pte_t *pmd = ttb_buff;
+		int i;
 
-                printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n",
+		printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n",
                 		ttb_buff);
-                ASSERT((read_mmfr0() & 0xf) >= 5);
-
-                /*
-                 * Set MAIR
-                 * See B4.1.104 of ARMv7 Architecture Reference Manual
-                 */
-                write_mair0(
-                        0x00 << (MAIR_INDX_NC*8) | /* Strongly-ordered,
-                         	 	 	    * Non-Cacheable */
-                        0xaa << (MAIR_INDX_WT*8) | /* Write-Thru,
-                         	 	 	    * Read-Allocate */
-                        0xff << (MAIR_INDX_WB*8)   /* Write-Back,
-                         	 	 	    * Read/Write-Allocate */
-                        );
-
-                /*
-                 * Set up L1 table
-                 * Once set here, L1 table won't be modified by coreboot.
-                 * See B3.6.1 of ARMv7 Architecture Reference Manual
-                 */
-                for (i = 0; i < 4; i++) {
-                        pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) |
-                                ATTR_NEXTLEVEL;
-                        pmd += BLOCK_SIZE / PAGE_SIZE;
-                }
-
-                /*
-                 * Set TTBR0
-                 */
-                write_ttbr0((uintptr_t)pgd_buff);
-        } else {
-                printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff);
-
-                /*
-                 * Translation table base 0 address is in bits 31:14-N, where N
-                 * is given by bits 2:0 in TTBCR (which we set to 0). All lower
-                 * bits in this register should be zero for coreboot.
-                 */
-                write_ttbr0((uintptr_t)ttb_buff);
-        }
+		ASSERT((read_mmfr0() & 0xf) >= 5);
+
+		/*
+		 * Set MAIR
+		 * See B4.1.104 of ARMv7 Architecture Reference Manual
+		 */
+		write_mair0(
+			0x00 << (MAIR_INDX_NC*8) | /* Strongly-ordered,
+						    * Non-Cacheable */
+			0xaa << (MAIR_INDX_WT*8) | /* Write-Thru,
+						    * Read-Allocate */
+			0xff << (MAIR_INDX_WB*8)   /* Write-Back,
+						    * Read/Write-Allocate */
+		);
+
+		/*
+		 * Set up L1 table
+		 * Once set here, L1 table won't be modified by coreboot.
+		 * See B3.6.1 of ARMv7 Architecture Reference Manual
+		 */
+		for (i = 0; i < 4; i++) {
+			pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) |
+			        ATTR_NEXTLEVEL;
+			pmd += BLOCK_SIZE / PAGE_SIZE;
+		}
+
+		/*
+		 * Set TTBR0
+		 */
+		write_ttbr0((uintptr_t)pgd_buff);
+	} else {
+		printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff);
+
+		/*
+		 * Translation table base 0 address is in bits 31:14-N, where N
+		 * is given by bits 2:0 in TTBCR (which we set to 0). All lower
+		 * bits in this register should be zero for coreboot.
+		 */
+		write_ttbr0((uintptr_t)ttb_buff);
+	}
 
 	/*
 	 * Set TTBCR
diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c
index 53ca2b3054f8..a3b1d0c13cc0 100644
--- a/src/arch/arm/armv7/thread.c
+++ b/src/arch/arm/armv7/thread.c
@@ -55,7 +55,7 @@ void arch_prepare_thread(struct thread *t,
 	 * hunting for (e.g.) misaligned stacks or other such
 	 * weirdness. The -1 is because we already pushed lr.
 	 */
-	for (i = 0; i < sizeof(struct pushed_regs)/sizeof(u32)-1; i++)
+	for (i = 0; i < sizeof(struct pushed_regs) / sizeof(u32) - 1; i++)
 		stack = push_stack(stack, poison++);
 
 	t->stack_current = stack;
@@ -103,7 +103,7 @@ switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack)
 	 * |    R4      | <-- sp + 0x00
 	 * +------------+
 	 */
-        asm volatile (
+	asm volatile (
 	/* save context. */
 	"push {r4-r11,lr}\n\t"
 	/* Save the current stack */
diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h
index 73ae89fe3ea8..d70622f959ea 100644
--- a/src/arch/arm/include/armv7/arch/cpu.h
+++ b/src/arch/arm/include/armv7/arch/cpu.h
@@ -39,9 +39,9 @@ struct cpu_info {
 };
 
 struct cpuinfo_arm {
-        uint8_t    arm;            /* CPU family */
-        uint8_t    arm_vendor;     /* CPU vendor */
-        uint8_t    arm_model;
+	uint8_t    arm;            /* CPU family */
+	uint8_t    arm_vendor;     /* CPU vendor */
+	uint8_t    arm_model;
 };
 
 #endif
diff --git a/src/arch/arm64/transition_asm.S b/src/arch/arm64/transition_asm.S
index 8fd629a8af7a..8e61246db17e 100644
--- a/src/arch/arm64/transition_asm.S
+++ b/src/arch/arm64/transition_asm.S
@@ -124,8 +124,8 @@ ENDPROC(exc_prologue)
  * x0 = regs structure
  */
 ENTRY(trans_switch)
-	msr	 SPSel, #SPSR_USE_L
-        b        exc_exit
+	msr	SPSel, #SPSR_USE_L
+	b	exc_exit
 ENDPROC(trans_switch)
 
 /*
diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h
index 7e8ec63bae1e..bc7b1962a35a 100644
--- a/src/arch/riscv/include/arch/cpu.h
+++ b/src/arch/riscv/include/arch/cpu.h
@@ -37,9 +37,9 @@ struct cpu_info {
 };
 
 struct cpuinfo_riscv {
-        uint8_t    riscv;            /* CPU family */
-        uint8_t    riscv_vendor;     /* CPU vendor */
-        uint8_t    riscv_model;
+	uint8_t    riscv;            /* CPU family */
+	uint8_t    riscv_vendor;     /* CPU vendor */
+	uint8_t    riscv_model;
 };
 
 #endif
diff --git a/src/arch/riscv/include/arch/hlt.h b/src/arch/riscv/include/arch/hlt.h
index de2f25c5aff0..da0277821b27 100644
--- a/src/arch/riscv/include/arch/hlt.h
+++ b/src/arch/riscv/include/arch/hlt.h
@@ -13,5 +13,5 @@
 
 static inline __attribute__((always_inline)) void hlt(void)
 {
-        while(1);
+	while (1);
 }
diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c
index 6b9c091e8e09..c55611be1139 100644
--- a/src/arch/x86/acpigen.c
+++ b/src/arch/x86/acpigen.c
@@ -339,8 +339,8 @@ void acpigen_write_scope(const char *name)
 void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len)
 {
 /*
-        Processor (\_PR.CPUcpuindex, cpuindex, pblock_addr, pblock_len)
-        {
+	Processor (\_PR.CPUcpuindex, cpuindex, pblock_addr, pblock_len)
+	{
 */
 	char pscope[16];
 	/* processor op */
@@ -359,26 +359,26 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len)
 void acpigen_write_empty_PCT(void)
 {
 /*
-    Name (_PCT, Package (0x02)
-    {
-        ResourceTemplate ()
-        {
-            Register (FFixedHW,
-                0x00,               // Bit Width
-                0x00,               // Bit Offset
-                0x0000000000000000, // Address
-                ,)
-        },
-
-        ResourceTemplate ()
-        {
-            Register (FFixedHW,
-                0x00,               // Bit Width
-                0x00,               // Bit Offset
-                0x0000000000000000, // Address
-                ,)
-        }
-    })
+	Name (_PCT, Package (0x02)
+	{
+		ResourceTemplate ()
+		{
+			Register (FFixedHW,
+				0x00,               // Bit Width
+				0x00,               // Bit Offset
+				0x0000000000000000, // Address
+				,)
+		},
+
+		ResourceTemplate ()
+		{
+			Register (FFixedHW,
+				0x00,               // Bit Width
+				0x00,               // Bit Offset
+				0x0000000000000000, // Address
+				,)
+		}
+	})
 */
 	static char stream[] = {
 		0x08, 0x5F, 0x50, 0x43, 0x54, 0x12, 0x2C,	/* 00000030    "0._PCT.," */
@@ -395,26 +395,26 @@ void acpigen_write_empty_PCT(void)
 void acpigen_write_empty_PTC(void)
 {
 /*
-    Name (_PTC, Package (0x02)
-    {
-        ResourceTemplate ()
-        {
-            Register (FFixedHW,
-                0x00,               // Bit Width
-                0x00,               // Bit Offset
-                0x0000000000000000, // Address
-                ,)
-        },
-
-        ResourceTemplate ()
-        {
-            Register (FFixedHW,
-                0x00,               // Bit Width
-                0x00,               // Bit Offset
-                0x0000000000000000, // Address
-                ,)
-        }
-    })
+	Name (_PTC, Package (0x02)
+	{
+		ResourceTemplate ()
+		{
+			Register (FFixedHW,
+				0x00,               // Bit Width
+				0x00,               // Bit Offset
+				0x0000000000000000, // Address
+				,)
+		},
+
+		ResourceTemplate ()
+		{
+			Register (FFixedHW,
+				0x00,               // Bit Width
+				0x00,               // Bit Offset
+				0x0000000000000000, // Address
+				,)
+		}
+	})
 */
 	acpi_addr_t addr = {
 		.space_id   = ACPI_ADDRESS_SPACE_FIXED,
@@ -478,10 +478,10 @@ void acpigen_write_STA(uint8_t status)
 void acpigen_write_PPC(u8 nr)
 {
 /*
-    Method (_PPC, 0, NotSerialized)
-    {
-        Return (nr)
-    }
+	Method (_PPC, 0, NotSerialized)
+	{
+		Return (nr)
+	}
 */
 	acpigen_write_method("_PPC", 0);
 	/* return */
@@ -498,10 +498,10 @@ void acpigen_write_PPC(u8 nr)
 void acpigen_write_PPC_NVS(void)
 {
 /*
-    Method (_PPC, 0, NotSerialized)
-    {
-        Return (PPCM)
-    }
+	Method (_PPC, 0, NotSerialized)
+	{
+		Return (PPCM)
+	}
 */
 	acpigen_write_method("_PPC", 0);
 	/* return */
@@ -514,12 +514,12 @@ void acpigen_write_PPC_NVS(void)
 void acpigen_write_TPC(const char *gnvs_tpc_limit)
 {
 /*
-    // Sample _TPC method
-    Method (_TPC, 0, NotSerialized)
-    {
-        Return (\TLVL)
-    }
- */
+	// Sample _TPC method
+	Method (_TPC, 0, NotSerialized)
+	{
+		Return (\TLVL)
+	}
+*/
 	acpigen_write_method("_TPC", 0);
 	acpigen_emit_byte(0xa4);		/* ReturnOp */
 	acpigen_emit_namestring(gnvs_tpc_limit);
@@ -611,13 +611,13 @@ void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, u3
 void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list)
 {
 /*
-    Sample _TSS package with 100% and 50% duty cycles
-    Name (_TSS, Package (0x02)
-    {
-        Package(){100, 1000, 0, 0x00, 0)
-        Package(){50, 520, 0, 0x18, 0)
-    })
- */
+	Sample _TSS package with 100% and 50% duty cycles
+	Name (_TSS, Package (0x02)
+	{
+		Package(){100, 1000, 0, 0x00, 0)
+		Package(){50, 520, 0, 0x18, 0)
+	})
+*/
 	int i;
 	acpi_tstate_t *tstate = tstate_list;