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| author | Julius Werner <jwerner@chromium.org> | 2022-11-30 16:18:01 -0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2022-12-22 15:34:28 +0000 |
| commit | 9a9b2778a1f04ba5d570de154f4b6f38f3b5807a (patch) | |
| tree | ce5c6fcc45240198711ab0f159a543bab6d629b6 /src/commonlib | |
| parent | ad6c407927a2aa05cb7ecb47c833b230c227db36 (diff) | |
| download | coreboot-9a9b2778a1f04ba5d570de154f4b6f38f3b5807a.tar.gz coreboot-9a9b2778a1f04ba5d570de154f4b6f38f3b5807a.tar.bz2 coreboot-9a9b2778a1f04ba5d570de154f4b6f38f3b5807a.zip | |
coreboot_tables: Make existing alignment conventions more explicit
There seem to be some recurring vague concerns about the alignment of
coreboot table entries. While the existing implementation has been
producing tables with a well-defined alignment (4 bytes) for a long
time, the code doesn't always make it very clear. This patch adds an
explicit constant to codify that alignment, assertions to check it after
each entry, and adds explicit padding to the few entry structures that
were relying on compiler padding to return a correct sizeof() value.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iaeef29ef255047a855066469e03b5481812e5975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70158
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
Diffstat (limited to 'src/commonlib')
| -rw-r--r-- | src/commonlib/include/commonlib/coreboot_tables.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 6b5eb59cf8ce..76dce0a41be1 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -95,6 +95,9 @@ enum { LB_TAG_OPTION_CHECKSUM = 0x00cc, }; +/* All table entry base addresses and sizes must be 4-byte aligned. */ +#define LB_ENTRY_ALIGN 4 + /* Since coreboot is usually compiled 32bit, gcc will align 64bit * types to 32bit boundaries. If the coreboot table is dumped on a * 64bit system, a uint64_t would be aligned to 64bit boundaries, @@ -104,7 +107,7 @@ enum { * to ensure compatibility. */ -typedef __aligned(4) uint64_t lb_uint64_t; +typedef __aligned(LB_ENTRY_ALIGN) uint64_t lb_uint64_t; struct lb_header { uint8_t signature[4]; /* LBIO */ @@ -203,6 +206,7 @@ struct lb_console { uint32_t tag; uint32_t size; uint16_t type; + uint8_t pad[2]; }; #define LB_TAG_CONSOLE_SERIAL8250 0 @@ -288,6 +292,7 @@ struct lb_framebuffer { uint8_t reserved_mask_pos; uint8_t reserved_mask_size; uint8_t orientation; + uint8_t pad[2]; }; struct lb_gpio { @@ -553,6 +558,7 @@ struct lb_tpm_physical_presence { uint32_t ppi_address; /* Address of ACPI PPI communication buffer */ uint8_t tpm_version; /* 1: TPM1.2, 2: TPM2.0 */ uint8_t ppi_version; /* BCD encoded */ + uint8_t pad[2]; }; |