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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-24 08:03:37 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-27 13:50:11 +0200 |
| commit | ae738acdc5f02d232e035538c67d63ba19b9ccaa (patch) | |
| tree | 862a877545dad919c698b48381a115bd15130fcc /src/cpu/x86/Kconfig | |
| parent | 7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b (diff) | |
| download | coreboot-ae738acdc5f02d232e035538c67d63ba19b9ccaa.tar.gz coreboot-ae738acdc5f02d232e035538c67d63ba19b9ccaa.tar.bz2 coreboot-ae738acdc5f02d232e035538c67d63ba19b9ccaa.zip | |
cpu/x86: Support CPUs without rdmsr/wrmsr instructions
Quark does not support the rdmsr and wrmsr instructions. In this case
use a SOC specific routine to support the setting of the MTRRs. Migrate
the code from FSP 1.1 to be x86 CPU common.
Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c. Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.
TEST=Build and run on Galileo Gen2
Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/x86/Kconfig')
| -rw-r--r-- | src/cpu/x86/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 74d87e2e9fd2..54a1fefab319 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -153,3 +153,10 @@ config BOOT_MEDIA_SPI_BUS depends on SPI_FLASH help Most x86 systems which boot from SPI flash boot using bus 0. + +config SOC_SETS_MSRS + bool + default n + help + The SoC requires different access methods for reading and writing + the MSRs. Use SoC specific routines to handle the MSR access. |