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| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2021-03-22 19:59:18 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-15 10:56:13 +0000 |
| commit | 26ab9bfeb53a5d73ff4fdb01c8a15417a2f76876 (patch) | |
| tree | 635f0ce598d308c13cb36845702240d1dcd0b47a /src/cpu/x86/lapic | |
| parent | 5c9bacca32c4554db0d2f04d371525c20488fac4 (diff) | |
| download | coreboot-26ab9bfeb53a5d73ff4fdb01c8a15417a2f76876.tar.gz coreboot-26ab9bfeb53a5d73ff4fdb01c8a15417a2f76876.tar.bz2 coreboot-26ab9bfeb53a5d73ff4fdb01c8a15417a2f76876.zip | |
*x86: Support x2apic mode
Implement x2apic mode as existing code only supports apic mode.
Use info from LAPIC_BASE_MSR (LAPIC_BASE_MSR_X2APIC_MODE) to check
if apic mode or x2apic mode and implement x2apic mode according to
x2apic specfication.
Reference:
https://software.intel.com/content/www/us/en/develop/download/intel-64-architecture-x2apic-specification.html
BUG=None
BRANCH=None
TEST=boot to OS and check apic mode
cat /proc/cpuinfo | grep "apicid"
ex) can see apicid bigger than 255
apicid : 256
apicid : 260
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I0bb729b0521fb9dc38b7981014755daeaf9ca817
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51723
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/x86/lapic')
| -rw-r--r-- | src/cpu/x86/lapic/lapic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 988d664c94a7..a5b4cd504710 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -47,6 +47,6 @@ void lapic_virtual_wire_mode_init(void) LAPIC_DELIVERY_MODE_NMI) ); - printk(BIOS_DEBUG, " apic_id: 0x%02x ", lapicid()); + printk(BIOS_DEBUG, " apic_id: 0x%x ", lapicid()); printk(BIOS_INFO, "done.\n"); } |