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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-10-20 14:41:27 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-05-23 12:33:17 +0000 |
| commit | 57e36a3320837729b6b20b0c4e44572898d0860f (patch) | |
| tree | cf1a410bab1a927b3d57fbeede5d4cc967722764 /src/cpu | |
| parent | 93791db23e475b3b5ab1175fc6d50418df937ad7 (diff) | |
| download | coreboot-57e36a3320837729b6b20b0c4e44572898d0860f.tar.gz coreboot-57e36a3320837729b6b20b0c4e44572898d0860f.tar.bz2 coreboot-57e36a3320837729b6b20b0c4e44572898d0860f.zip | |
cpu/intel/model_206ax: Program Ivy Bridge defaults for MSR_PKGC_IRTL
Ivy Bridge has lower latencies than Sandy Bridge has. Update MSRs
MSR_PKGC_IRTL with values from BWG.
Test: Lenovo X220 still boots.
Change-Id: Ib307e3b191ba68e016cc348f82e2dccf1dc9ae16
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78609
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/model_206ax/model_206ax_init.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index cdec3a6f468d..8a4dd3f19aa6 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -190,17 +190,26 @@ static void configure_c_states(struct device *dev) /* C3 Interrupt Response Time Limit */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50; + if (IS_IVY_CPU(cpu_get_cpuid())) + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x3b; + else + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50; wrmsr(MSR_PKGC3_IRTL, msr); /* C6 Interrupt Response Time Limit */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68; + if (IS_IVY_CPU(cpu_get_cpuid())) + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50; + else + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68; wrmsr(MSR_PKGC6_IRTL, msr); /* C7 Interrupt Response Time Limit */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D; + if (IS_IVY_CPU(cpu_get_cpuid())) + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x57; + else + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D; wrmsr(MSR_PKGC7_IRTL, msr); /* Primary Plane Current Limit (Icc) */ |