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| author | Raul E Rangel <rrangel@chromium.org> | 2021-07-16 15:06:56 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-20 16:52:35 +0000 |
| commit | ad5307e46c63a8f293f5588f33ef3bade6f191e5 (patch) | |
| tree | fe6f5b317111bf1b7e820ee52b8e9bf5d4df6b3d /src/device | |
| parent | 69cb69f35fc3c5fa1e75b49ce0f9358acbc42ea8 (diff) | |
| download | coreboot-ad5307e46c63a8f293f5588f33ef3bade6f191e5.tar.gz coreboot-ad5307e46c63a8f293f5588f33ef3bade6f191e5.tar.bz2 coreboot-ad5307e46c63a8f293f5588f33ef3bade6f191e5.zip | |
device/pci_rom: Make ON_DEVICE_ROM_LOAD condition truthy
Truthy conditions are easier to reason about.
BUG=none
TEST=Boot guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I229c3e90f5122d6191b28f9b4b6de79ac2fcb627
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/device')
| -rw-r--r-- | src/device/pci_rom.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index fe7c1cfdf029..895c5b773733 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -68,11 +68,7 @@ struct rom_header *pci_rom_probe(const struct device *dev) if (rom_header) { printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n", dev_path(dev), rom_header); - } else if (!CONFIG(ON_DEVICE_ROM_LOAD)) { - printk(BIOS_DEBUG, "PCI Option ROM loading disabled for %s\n", - dev_path(dev)); - return NULL; - } else { + } else if (CONFIG(ON_DEVICE_ROM_LOAD)) { uintptr_t rom_address; rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); @@ -93,6 +89,10 @@ struct rom_header *pci_rom_probe(const struct device *dev) printk(BIOS_DEBUG, "Option ROM address for %s = %lx\n", dev_path(dev), (unsigned long)rom_address); rom_header = (struct rom_header *)rom_address; + } else { + printk(BIOS_DEBUG, "PCI Option ROM loading disabled for %s\n", + dev_path(dev)); + return NULL; } printk(BIOS_SPEW, |