diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-10-12 11:23:33 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-16 00:12:35 +0000 |
| commit | 78130663e5cac7939ee04f97ac1c7fcecde23820 (patch) | |
| tree | a7281c09543deaf0536833201df03ecbd632ee97 /src/drivers/uart | |
| parent | 30f9b953a8ddf3d283e63f9bc1f95605d10a6491 (diff) | |
| download | coreboot-78130663e5cac7939ee04f97ac1c7fcecde23820.tar.gz coreboot-78130663e5cac7939ee04f97ac1c7fcecde23820.tar.bz2 coreboot-78130663e5cac7939ee04f97ac1c7fcecde23820.zip | |
drivers/uart8250mem: Check for zero base address
Before adding a new UART to the coreboot/lb table, verify that it
has a non-zero base address. This is consistent with all other
functions that use the uart_platform_base() function.
This was tested on google/kahlee by using an invalid UART number
and forcing the base address to 0. Execution was able to complete
through depthcharge and into the OS.
Change-Id: I6d8183a461f0fedc254bf88de5ec96629a2a80ef
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21996
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/uart')
| -rw-r--r-- | src/drivers/uart/uart8250mem.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index f293230e2e94..9eb50cb4b156 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -154,6 +154,8 @@ void uart_fill_lb(void *data) struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + if (!serial.baseaddr) + return; serial.baud = CONFIG_TTYS0_BAUD; if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) serial.regwidth = sizeof(uint32_t); |