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| author | Vadim Bendebury <vbendeb@chromium.org> | 2015-01-09 16:54:19 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-17 09:53:39 +0200 |
| commit | 9dccf1c40bc2543ad12f6a5af9daea8d0ef0ddfa (patch) | |
| tree | d1748e53dd45497dfda184d3452a0e7fa96d6035 /src/include/boot | |
| parent | f7da3d2a94dc996235b296569d1eff77842fe361 (diff) | |
| download | coreboot-9dccf1c40bc2543ad12f6a5af9daea8d0ef0ddfa.tar.gz coreboot-9dccf1c40bc2543ad12f6a5af9daea8d0ef0ddfa.tar.bz2 coreboot-9dccf1c40bc2543ad12f6a5af9daea8d0ef0ddfa.zip | |
uart: pass register width in the coreboot table
Some SOCs (like pistachio, for instance) provide an 8250 compatible
UART, which has the same register layout, but mapped to a bus of a
different width.
Instead of adding a new driver for these controllers, it is better to
have coreboot report UART register width to libpayload, and have it
adjust the offsets accordingly when accessing the UART.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=with the rest of the patches integrated depthcharge console messages
show up when running on the FPGA board
Change-Id: I30b742146069450941164afb04641b967a214d6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42
Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240027
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9738
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/include/boot')
| -rw-r--r-- | src/include/boot/coreboot_tables.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 74851b2fbbb2..7b5da64ec3db 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -159,6 +159,7 @@ struct lb_serial { uint32_t type; uint32_t baseaddr; uint32_t baud; + uint32_t regwidth; }; #define LB_TAG_CONSOLE 0x0010 |