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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-06-07 00:17:06 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-09 16:33:38 +0200 |
| commit | 87f7588c50225ef3d5c87de99635cc4fb9571f89 (patch) | |
| tree | 00cb212b343151b60f3e6b00046db13cc0e51fcd /src/include/device/dram | |
| parent | 459d2198ebf855596f41a747719baadbde12d730 (diff) | |
| download | coreboot-87f7588c50225ef3d5c87de99635cc4fb9571f89.tar.gz coreboot-87f7588c50225ef3d5c87de99635cc4fb9571f89.tar.bz2 coreboot-87f7588c50225ef3d5c87de99635cc4fb9571f89.zip | |
device/dram/ddr2.c: Fix is_registered_ddr2
Type 0x10 is mini RDIMM according to JEDEC DDR2 SPD
specifications.
Change-Id: I6d35bd74961326ebd9225f044313b107aca24bda
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/include/device/dram')
| -rw-r--r-- | src/include/device/dram/ddr2.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 7f59a7a7c146..8ea80b986aba 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -75,7 +75,7 @@ enum spd_dimm_type { SPD_DIMM_TYPE_72B_SO_CDIMM = 0x06, SPD_DIMM_TYPE_72B_SO_RDIMM = 0x07, SPD_DIMM_TYPE_MICRO_DIMM = 0x08, - SPD_DIMM_TYPE_MINI_DIMM = 0x10, + SPD_DIMM_TYPE_MINI_RDIMM = 0x10, SPD_DIMM_TYPE_MINI_UDIMM = 0x20, /* Masks to bits 5:0 to give the dimm type */ SPD_DIMM_TYPE_MASK = 0x3f, |