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| author | Elyes Haouas <ehaouas@noos.fr> | 2024-05-06 10:08:51 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-05-07 10:53:18 +0000 |
| commit | 0f45e17f564a657ddf9804124e4e30da0edb1d13 (patch) | |
| tree | 94482f30d5d59c8b2d8bf4af1feefe9b734d100f /src/include | |
| parent | 239347a90934deb77443869b6544c31f9b261733 (diff) | |
| download | coreboot-0f45e17f564a657ddf9804124e4e30da0edb1d13.tar.gz coreboot-0f45e17f564a657ddf9804124e4e30da0edb1d13.tar.bz2 coreboot-0f45e17f564a657ddf9804124e4e30da0edb1d13.zip | |
dram/ddr5: Use the same naming convention as DDR{2,3,4}
Change-Id: I2cc38926b56315d4a828311917ff58051b34b777
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/device/dram/ddr5.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/include/device/dram/ddr5.h b/src/include/device/dram/ddr5.h index 37182da365c3..78d18b24f8ab 100644 --- a/src/include/device/dram/ddr5.h +++ b/src/include/device/dram/ddr5.h @@ -15,20 +15,20 @@ /** Maximum SPD size supported */ #define SPD_SIZE_MAX_DDR5 1024 -enum ddr5_module_type { - DDR5_SPD_RDIMM = 0x01, - DDR5_SPD_UDIMM = 0x02, - DDR5_SPD_SODIMM = 0x03, - DDR5_SPD_LRDIMM = 0x04, - DDR5_SPD_MINI_RDIMM = 0x05, - DDR5_SPD_MINI_UDIMM = 0x06, - DDR5_SPD_72B_SO_UDIMM = 0x08, - DDR5_SPD_72B_SO_RDIMM = 0x09, - DDR5_SPD_SOLDERED_DOWN = 0x0b, - DDR5_SPD_16B_SO_DIMM = 0x0c, - DDR5_SPD_32B_SO_RDIMM = 0x0d, - DDR5_SPD_1DPC = 0x0e, - DDR5_SPD_2DPC = 0x0f, +enum spd_dimm_type_ddr5 { + SPD_DDR5_DIMM_TYPE_RDIMM = 0x01, + SPD_DDR5_DIMM_TYPE_UDIMM = 0x02, + SPD_DDR5_DIMM_TYPE_SODIMM = 0x03, + SPD_DDR5_DIMM_TYPE_LRDIMM = 0x04, + SPD_DDR5_DIMM_TYPE_MINI_RDIMM = 0x05, + SPD_DDR5_DIMM_TYPE_MINI_UDIMM = 0x06, + SPD_DDR5_DIMM_TYPE_72B_SO_UDIMM = 0x08, + SPD_DDR5_DIMM_TYPE_72B_SO_RDIMM = 0x09, + SPD_DDR5_DIMM_TYPE_SOLDERED_DOWN = 0x0b, + SPD_DDR5_DIMM_TYPE_16B_SO_DIMM = 0x0c, + SPD_DDR5_DIMM_TYPE_32B_SO_RDIMM = 0x0d, + SPD_DDR5_DIMM_TYPE_1DPC = 0x0e, + SPD_DDR5_DIMM_TYPE_2DPC = 0x0f, }; /** |