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| author | Elyes Haouas <ehaouas@noos.fr> | 2024-05-06 05:11:28 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-05-07 10:52:44 +0000 |
| commit | 78ba7a7865ed1f60c7f55bfcced305bc8fbdc9c6 (patch) | |
| tree | 876ce8b879c63c3a121701047d35346388192176 /src/include | |
| parent | 0f3316bc71aab50dbd8464ee2fb5b680947f2ca5 (diff) | |
| download | coreboot-78ba7a7865ed1f60c7f55bfcced305bc8fbdc9c6.tar.gz coreboot-78ba7a7865ed1f60c7f55bfcced305bc8fbdc9c6.tar.bz2 coreboot-78ba7a7865ed1f60c7f55bfcced305bc8fbdc9c6.zip | |
device/dram/ddr{3,4}: Rename spd_raw_data for specific DDR
Rename different spd_raw_data[] for DDR3 and DDR4.
This is to solve the conflict when we include both "ddr3.h" and ddr4.h"
for example here: src/device/dram/spd.c.
Otherwise, it won't compile as DDR3 and DDR4 have different
spd_raw_data[] size.
Change-Id: I46597fe82790410fbb53d60e04b7fdffb7b0094a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/device/dram/ddr3.h | 6 | ||||
| -rw-r--r-- | src/include/device/dram/ddr4.h | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 6efe0494dfbf..65977b49c167 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -153,15 +153,15 @@ enum ddr3_xmp_profile { DDR3_XMP_PROFILE_2 = 1, }; -typedef u8 spd_raw_data[256]; +typedef u8 spd_ddr3_raw_data[SPD_SIZE_MAX_DDR3]; u16 spd_ddr3_calc_crc(u8 *spd, int len); u16 spd_ddr3_calc_unique_crc(u8 *spd, int len); -int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd_data); +int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd_data); int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type); void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm); int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, - spd_raw_data spd, + spd_ddr3_raw_data spd, enum ddr3_xmp_profile profile); enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected_freq, diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index 72102125206e..da7359a253a1 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -64,9 +64,9 @@ struct dimm_attr_ddr4_st { bool ecc_extension; }; -typedef u8 spd_raw_data[512]; +typedef u8 spd_ddr4_raw_data[SPD_SIZE_MAX_DDR4]; -int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd); +int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_ddr4_raw_data spd); enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, |