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| author | Scott Chao <scott_chao@wistron.corp-partner.google.com> | 2022-04-18 10:40:18 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-27 12:26:52 +0000 |
| commit | ea99f0dcea1b56f6eb6318c9fbf14883031460af (patch) | |
| tree | be6403089dd22a3ed1192b6203e647642eec6625 /src/lib | |
| parent | c3e4f6700586245d009937c44c78b3d9614785b7 (diff) | |
| download | coreboot-ea99f0dcea1b56f6eb6318c9fbf14883031460af.tar.gz coreboot-ea99f0dcea1b56f6eb6318c9fbf14883031460af.tar.bz2 coreboot-ea99f0dcea1b56f6eb6318c9fbf14883031460af.zip | |
lib: Add LPDDR5 DRAM type
BUG=b:229437061
TEST=Not seeing default msg "Defaulting to using DDR4 params." with
this CL.
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I98ba9e87b1a093b93434334a75c9a9252effa933
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/lib')
| -rw-r--r-- | src/lib/spd_bin.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 1b236b0e8f4d..823f717910a0 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -34,6 +34,7 @@ static bool use_ddr4_params(int dram_type) case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_DDR5: + case SPD_DRAM_LPDDR5: case SPD_DRAM_LPDDR4: case SPD_DRAM_LPDDR4X: return true; @@ -165,6 +166,7 @@ static void spd_get_name(const uint8_t spd[], int type, const char **spd_name, s case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_DDR5: + case SPD_DRAM_LPDDR5: case SPD_DRAM_LPDDR4: case SPD_DRAM_LPDDR4X: if (spd[DDR4_SPD_PART_OFF]) { |