AGESA boards: Split dispatcher to romstage and ramstage

The way dispatcher table is set up prevents linker from
optimizing unused code away, we currently have raminit in ramstage.

Optimize this manually by configuring AGESA_ENTRY booleans for
romstage and ramstage separately. This will remove references in
FuncParamsInfo and DispatchTable -arrays.

All boards now include multi-core dispatcher, it has minimal footprint:
  AGESA_ENTRY_LATE_RUN_AP_TASK

ACPI S3 support depends on HAVE_ACPI_RESUME being enabled:
  AGESA_ENTRY_INIT_RESUME
  AGESA_ENTRY_INIT_LATE_RESTORE
  AGESA_ENTRY_INIT_S3SAVE

Disabled for all boards as it was not used:
  AGESA_ENTRY_INIT_GENERAL_SERVICES

Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14417
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

9 files changed, 0 insertions, 129 deletions

diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c
index 6ac5ed826c15..efed4b778ccd 100644
--- a/src/mainboard/amd/dinar/buildOpts.c
+++ b/src/mainboard/amd/dinar/buildOpts.c
@@ -26,7 +26,6 @@
  */
 #include <stdlib.h>
 #include "AGESA.h"
-#include "CommonReturns.h"
 #include "Filecode.h"
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 //#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
@@ -153,24 +152,9 @@
 #define BLDCFG_PSTATE_HPC_MODE                    FALSE
 
 #define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap
-/*
- * Agesa entry points used in this implementation.
- */
 /*  Process the options...
  * This file include MUST occur AFTER the user option selection settings
  */
-#define AGESA_ENTRY_INIT_RESET                    TRUE//FALSE
-#define AGESA_ENTRY_INIT_RECOVERY                 FALSE
-#define AGESA_ENTRY_INIT_EARLY                    TRUE
-#define AGESA_ENTRY_INIT_POST                     TRUE
-#define AGESA_ENTRY_INIT_ENV                      TRUE
-#define AGESA_ENTRY_INIT_MID                      TRUE
-#define AGESA_ENTRY_INIT_LATE                     TRUE
-#define AGESA_ENTRY_INIT_S3SAVE                   TRUE
-#define AGESA_ENTRY_INIT_RESUME                   TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
-#define AGESA_ENTRY_LATE_RUN_AP_TASK              TRUE
 
 
 /*****************************************************************************
@@ -395,7 +379,6 @@ CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] =
 #include "CreateStruct.h"
 #include "cpuFeatures.h"
 #include "Table.h"
-#include "CommonReturns.h"
 #include "cpuEarlyInit.h"
 #include "cpuLateInit.h"
 #include "GnbInterfaceStub.h"
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index b4651b6bb3d0..ffaf79a7fb3d 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -101,20 +101,6 @@
 #define BLDOPT_REMOVE_GFX_RECOVERY		TRUE
 #define BLDOPT_REMOVE_EARLY_SAMPLES		TRUE
 
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET			TRUE
-#define AGESA_ENTRY_INIT_RECOVERY		FALSE
-#define AGESA_ENTRY_INIT_EARLY			TRUE
-#define AGESA_ENTRY_INIT_POST			TRUE
-#define AGESA_ENTRY_INIT_ENV			TRUE
-#define AGESA_ENTRY_INIT_MID			TRUE
-#define AGESA_ENTRY_INIT_LATE			TRUE
-#define AGESA_ENTRY_INIT_S3SAVE			TRUE
-#define AGESA_ENTRY_INIT_RESUME			TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE		FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES	FALSE
 
 #define BLDCFG_PCI_MMIO_BASE			CONFIG_MMCONF_BASE_ADDRESS
 #define BLDCFG_PCI_MMIO_SIZE			CONFIG_MMCONF_BUS_NUMBER
@@ -218,7 +204,6 @@
  * needed by the system.
  */
 #include "AGESA.h"
-#include "CommonReturns.h"
 
 /* The fixed MTRR values to be set after memory initialization. */
 CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c
index 153d8562cac6..106e1c1eca94 100644
--- a/src/mainboard/amd/olivehill/buildOpts.c
+++ b/src/mainboard/amd/olivehill/buildOpts.c
@@ -171,17 +171,6 @@
 /*  Process the options...
  * This file include MUST occur AFTER the user option selection settings
  */
-#define AGESA_ENTRY_INIT_RESET                    TRUE
-#define AGESA_ENTRY_INIT_RECOVERY                 FALSE
-#define AGESA_ENTRY_INIT_EARLY                    TRUE
-#define AGESA_ENTRY_INIT_POST                     TRUE
-#define AGESA_ENTRY_INIT_ENV                      TRUE
-#define AGESA_ENTRY_INIT_MID                      TRUE
-#define AGESA_ENTRY_INIT_LATE                     TRUE
-#define AGESA_ENTRY_INIT_S3SAVE                   TRUE
-#define AGESA_ENTRY_INIT_RESUME                   TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
 /*
  * Customized OEM build configurations for FCH component
  */
@@ -251,7 +240,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
 #include "CreateStruct.h"
 #include "cpuFeatures.h"
 #include "Table.h"
-#include "CommonReturns.h"
 #include "cpuEarlyInit.h"
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index e7ee47dedf2a..11d36bcc3161 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -172,17 +172,6 @@
 /*  Process the options...
  * This file include MUST occur AFTER the user option selection settings
  */
-#define AGESA_ENTRY_INIT_RESET                    TRUE
-#define AGESA_ENTRY_INIT_RECOVERY                 FALSE
-#define AGESA_ENTRY_INIT_EARLY                    TRUE
-#define AGESA_ENTRY_INIT_POST                     TRUE
-#define AGESA_ENTRY_INIT_ENV                      TRUE
-#define AGESA_ENTRY_INIT_MID                      TRUE
-#define AGESA_ENTRY_INIT_LATE                     TRUE
-#define AGESA_ENTRY_INIT_S3SAVE                   TRUE
-#define AGESA_ENTRY_INIT_RESUME                   TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
 /*
  * Customized OEM build configurations for FCH component
  */
@@ -252,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
 #include "CreateStruct.h"
 #include "cpuFeatures.h"
 #include "Table.h"
-#include "CommonReturns.h"
 #include "cpuEarlyInit.h"
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index 1ded047f6899..fe4e779626ab 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -101,20 +101,6 @@
 #define BLDOPT_REMOVE_GFX_RECOVERY				TRUE
 #define BLDOPT_REMOVE_EARLY_SAMPLES				TRUE
 
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET					TRUE
-#define AGESA_ENTRY_INIT_RECOVERY				FALSE
-#define AGESA_ENTRY_INIT_EARLY					TRUE
-#define AGESA_ENTRY_INIT_POST					TRUE
-#define AGESA_ENTRY_INIT_ENV					TRUE
-#define AGESA_ENTRY_INIT_MID					TRUE
-#define AGESA_ENTRY_INIT_LATE					TRUE
-#define AGESA_ENTRY_INIT_S3SAVE					TRUE
-#define AGESA_ENTRY_INIT_RESUME					TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE				TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES			TRUE
 
 #define BLDCFG_PCI_MMIO_BASE					CONFIG_MMCONF_BASE_ADDRESS
 #define BLDCFG_PCI_MMIO_SIZE					CONFIG_MMCONF_BUS_NUMBER
@@ -218,7 +204,6 @@
  * needed by the system.
  */
 #include "AGESA.h"
-#include "CommonReturns.h"
 
 /* The fixed MTRR values to be set after memory initialization. */
 CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index 7f07ea121083..2f696ef87c61 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -101,20 +101,6 @@
 #define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
 #define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
 
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET                    TRUE
-#define AGESA_ENTRY_INIT_RECOVERY                 FALSE
-#define AGESA_ENTRY_INIT_EARLY                    TRUE
-#define AGESA_ENTRY_INIT_POST                     TRUE
-#define AGESA_ENTRY_INIT_ENV                      TRUE
-#define AGESA_ENTRY_INIT_MID                      TRUE
-#define AGESA_ENTRY_INIT_LATE                     TRUE
-#define AGESA_ENTRY_INIT_S3SAVE                   TRUE
-#define AGESA_ENTRY_INIT_RESUME                   TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES         FALSE
 
 #define BLDCFG_PCI_MMIO_BASE                    CONFIG_MMCONF_BASE_ADDRESS
 #define BLDCFG_PCI_MMIO_SIZE                    CONFIG_MMCONF_BUS_NUMBER
@@ -218,7 +204,6 @@
  * needed by the system.
  */
 #include "AGESA.h"
-#include "CommonReturns.h"
 
 /* The fixed MTRR values to be set after memory initialization. */
 CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index a26f6971b348..45569df880bd 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -172,17 +172,6 @@
 /*  Process the options...
  * This file include MUST occur AFTER the user option selection settings
  */
-#define AGESA_ENTRY_INIT_RESET                    TRUE
-#define AGESA_ENTRY_INIT_RECOVERY                 FALSE
-#define AGESA_ENTRY_INIT_EARLY                    TRUE
-#define AGESA_ENTRY_INIT_POST                     TRUE
-#define AGESA_ENTRY_INIT_ENV                      TRUE
-#define AGESA_ENTRY_INIT_MID                      TRUE
-#define AGESA_ENTRY_INIT_LATE                     TRUE
-#define AGESA_ENTRY_INIT_S3SAVE                   TRUE
-#define AGESA_ENTRY_INIT_RESUME                   TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
 /*
  * Customized OEM build configurations for FCH component
  */
@@ -252,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
 #include "CreateStruct.h"
 #include "cpuFeatures.h"
 #include "Table.h"
-#include "CommonReturns.h"
 #include "cpuEarlyInit.h"
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
index 9abc6512fd18..40f1f9722781 100644
--- a/src/mainboard/amd/torpedo/buildOpts.c
+++ b/src/mainboard/amd/torpedo/buildOpts.c
@@ -27,7 +27,6 @@
 
 #include <stdlib.h>
 #include "AGESA.h"
-#include "CommonReturns.h"
 #include "Filecode.h"
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
@@ -83,20 +82,6 @@
 //For revision C single-link processors
 #define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX  TRUE
 
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET                    TRUE
-#define AGESA_ENTRY_INIT_RECOVERY                 FALSE
-#define AGESA_ENTRY_INIT_EARLY                    TRUE
-#define AGESA_ENTRY_INIT_POST                     TRUE
-#define AGESA_ENTRY_INIT_ENV                      TRUE
-#define AGESA_ENTRY_INIT_MID                      TRUE
-#define AGESA_ENTRY_INIT_LATE                     TRUE
-#define AGESA_ENTRY_INIT_S3SAVE                   TRUE
-#define AGESA_ENTRY_INIT_RESUME                   TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
 
 /*****************************************************************************
  *   Define the RELEASE VERSION string
@@ -230,7 +215,6 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
 #include "CreateStruct.h"
 #include "cpuFeatures.h"
 #include "Table.h"
-#include "CommonReturns.h"
 #include "cpuEarlyInit.h"
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index 7f07ea121083..2f696ef87c61 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -101,20 +101,6 @@
 #define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
 #define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
 
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET                    TRUE
-#define AGESA_ENTRY_INIT_RECOVERY                 FALSE
-#define AGESA_ENTRY_INIT_EARLY                    TRUE
-#define AGESA_ENTRY_INIT_POST                     TRUE
-#define AGESA_ENTRY_INIT_ENV                      TRUE
-#define AGESA_ENTRY_INIT_MID                      TRUE
-#define AGESA_ENTRY_INIT_LATE                     TRUE
-#define AGESA_ENTRY_INIT_S3SAVE                   TRUE
-#define AGESA_ENTRY_INIT_RESUME                   TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES         FALSE
 
 #define BLDCFG_PCI_MMIO_BASE                    CONFIG_MMCONF_BASE_ADDRESS
 #define BLDCFG_PCI_MMIO_SIZE                    CONFIG_MMCONF_BUS_NUMBER
@@ -218,7 +204,6 @@
  * needed by the system.
  */
 #include "AGESA.h"
-#include "CommonReturns.h"
 
 /* The fixed MTRR values to be set after memory initialization. */
 CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =