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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-28 18:50:26 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-15 11:23:23 +0000 |
| commit | ba5761a947cc7bd2f13454570e62cde57f4fbd08 (patch) | |
| tree | e451f8ec6491814d8793558b983adae8cbf8a4d8 /src/mainboard/asrock | |
| parent | 6d2d19de7453de04830163a234a970ea9eab386c (diff) | |
| download | coreboot-ba5761a947cc7bd2f13454570e62cde57f4fbd08.tar.gz coreboot-ba5761a947cc7bd2f13454570e62cde57f4fbd08.tar.bz2 coreboot-ba5761a947cc7bd2f13454570e62cde57f4fbd08.zip | |
cpu/intel/haswell: Factor out ACPI C-state values
There's no need to have them in the devicetree. ACPI generation can now
be simplified even further, and is done in subsequent commits.
Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46908
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock')
| -rw-r--r-- | src/mainboard/asrock/b85m_pro4/devicetree.cb | 7 | ||||
| -rw-r--r-- | src/mainboard/asrock/h81m-hds/devicetree.cb | 7 |
2 files changed, 0 insertions, 14 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 024d1f0e1f2c..43a65f819752 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -5,13 +5,6 @@ chip northbridge/intel/haswell device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 45119f9476e2..7b08af96d867 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -5,13 +5,6 @@ chip northbridge/intel/haswell device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end |