The new CBFS based build system requires the whole ROM to be accessible

in very early stages, otherwise the boot may hang like this because
the CBFS headers cannot be found/accessed:

  Uncompressing coreboot to RAM.
  Jumping to image.
  Check CBFS header at fffedfe0
  magic is ffffffff
  ERROR: No valid CBFS header found!
  CBFS:  Could not find file fallback/coreboot_ram
  Jumping to image.

This patch enables full ROM access on all 440BX boards right after the
serial init (and before CBFS headers are parsed).

Build-tested and runtime-tested on ASUS P2B-F.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 25 insertions, 0 deletions

diff --git a/src/mainboard/asus/p2b-d/auto.c b/src/mainboard/asus/p2b-d/auto.c
index 4857cd540f89..7371ba787056 100644
--- a/src/mainboard/asus/p2b-d/auto.c
+++ b/src/mainboard/asus/p2b-d/auto.c
@@ -31,6 +31,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
diff --git a/src/mainboard/asus/p2b-ds/auto.c b/src/mainboard/asus/p2b-ds/auto.c
index 141f444684e2..810d7e352bf5 100644
--- a/src/mainboard/asus/p2b-ds/auto.c
+++ b/src/mainboard/asus/p2b-ds/auto.c
@@ -31,6 +31,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
diff --git a/src/mainboard/asus/p2b-f/auto.c b/src/mainboard/asus/p2b-f/auto.c
index 86b075994937..76d14ae15de6 100644
--- a/src/mainboard/asus/p2b-f/auto.c
+++ b/src/mainboard/asus/p2b-f/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
diff --git a/src/mainboard/asus/p2b/auto.c b/src/mainboard/asus/p2b/auto.c
index fa027e112783..2dfdb2432f04 100644
--- a/src/mainboard/asus/p2b/auto.c
+++ b/src/mainboard/asus/p2b/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
diff --git a/src/mainboard/asus/p3b-f/auto.c b/src/mainboard/asus/p3b-f/auto.c
index c9c64fc8e55f..fb3169f8adb7 100644
--- a/src/mainboard/asus/p3b-f/auto.c
+++ b/src/mainboard/asus/p3b-f/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();