Add preliminary support for Bachmann electronic OT200

Linux boots fine :)

Change-Id: Ifda06e5220666534b87f528deae16d8b956c32b3
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/1225
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

1 files changed, 68 insertions, 0 deletions

diff --git a/src/mainboard/bachmann/ot200/irq_tables.c b/src/mainboard/bachmann/ot200/irq_tables.c
new file mode 100644
index 000000000000..7c3e08f3800d
--- /dev/null
+++ b/src/mainboard/bachmann/ot200/irq_tables.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Bachmann electronic GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+/* Platform IRQs */
+#define PIRQA 5
+#define PIRQB 9
+#define PIRQC 7
+#define PIRQD 10
+
+/* Map */
+#define M_PIRQA (1 << PIRQA)	/* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB)	/* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC)	/* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD)	/* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA  1		/* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB  2		/* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC  3		/* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD  4		/* Means Slot INTx# Connects To Chipset INTD# */
+
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,				/* u32 signature */
+	PIRQ_VERSION,				/* u16 version */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,	/* Max. number of devices on the bus */
+	0x00,					/* Interrupt router bus */
+	0x0f << 3,				/* Interrupt router dev */
+	0,					/* IRQs devoted exclusively to PCI usage */
+	0x100b,					/* Vendor */
+	0x2b,					/* Device */
+	0,					/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 	/* u8 rfu[11] */
+	0x20,					/* Checksum (has to be set to some value that
+						 * would give 0 after the sum of all bytes
+						 * for this structure (including checksum).
+						 */
+	{
+		/* bus,        dev | fn,   {link, bitmap},     {link, bitmap},     {link, bitmap},     {link, bitmap},      slot, rfu */
+		{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000},     {0x00, 0x0000},     {0x00, 0x0000}},     0x0, 0x0},	/* CPU */
+		{0x00, (0x0f << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
+		{0x00, (0x04 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000},     {0x00, 0x0000},     {0x00, 0x0000}},     0x0, 0x0},	/* ethernet */
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}