newconfig is no more.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 0 insertions, 271 deletions

diff --git a/src/mainboard/emulation/qemu-x86/Config.lb b/src/mainboard/emulation/qemu-x86/Config.lb
deleted file mode 100644
index 7357648411df..000000000000
--- a/src/mainboard/emulation/qemu-x86/Config.lb
+++ /dev/null
@@ -1,131 +0,0 @@
-## we don't use CONFIG_USE_DCACHE_RAM by default
-default CONFIG_USE_DCACHE_RAM=0
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-default CONFIG_ROM_SIZE = 256 * 1024 
-default CONFIG_ROM_SECTION_SIZE   = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_ROM_SECTION_OFFSET = CONFIG_ROM_SIZE - CONFIG_ROM_SECTION_SIZE
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default CONFIG_ROMBASE      = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
-##
-default CONFIG_XIP_ROM_SIZE=32*1024
-default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-
-## ALL dependencies for CONFIG_USE_DCACHE_RAM go here. 
-## That way, later, we can simply yank them if we wish. 
-## We include the old-fashioned entry code in the ! CONFIG_USE_DCACHE_RAM case. 
-## we do not use failover yet in this case. This is a work in progress. 
-if CONFIG_USE_DCACHE_RAM
-	##
-	##
-	mainboardinit arch/i386/init/entry.S
-	mainboardinit arch/i386/init/car.S
-	ldscript  /arch/i386/init/ldscript.ld
-
-	## The main code for the rom section is called rom.c
-	initobject rom.o
-else
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-		depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
-		action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-	end
-	
-	makerule ./failover.inc
-		depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-		action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-	end
-	
-	makerule ./auto.E 
-		depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-		action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-	end
-	makerule ./auto.inc 
-		depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-		action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-	end
-	
-	##
-	## Build our 16 bit and 32 bit coreboot entry code
-	##
-	mainboardinit cpu/x86/16bit/entry16.inc
-	mainboardinit cpu/x86/32bit/entry32.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-	ldscript /cpu/x86/32bit/entry32.lds
-
-	##
-	## Build our reset vector (This is where coreboot is entered)
-	##
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-	
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-
-	##
-	## Setup RAM
-	##
-	mainboardinit cpu/x86/fpu_enable.inc
-	mainboardinit ./auto.inc
-	
-	## the id string will be in cbfs. We will expect flashrom to parse cbfs for the idstring in future. 
-	##
-	## Include an id string (For safe flashing)
-	##
-	mainboardinit arch/i386/lib/id.inc
-	ldscript /arch/i386/lib/id.lds
-	
-##
-## end of CONFIG_USE_DCACHE_RAM bits. 
-##
-end
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip cpu/emulation/qemu-x86
-	device pci_domain 0 on 
-		device pci 0.0 on end
-
-		chip southbridge/intel/i82371eb # southbridge
-			device pci 01.0 on end
-			device pci 01.1 on end
-			register "ide0_enable" = "1"
-			register "ide1_enable" = "1"
-		end
-
-#		register "com1" = "{1}"
-#		register "com1" = "{1, 0, 0x3f8, 4}"
-	end
-end
diff --git a/src/mainboard/emulation/qemu-x86/Options.lb b/src/mainboard/emulation/qemu-x86/Options.lb
deleted file mode 100644
index e0671284a834..000000000000
--- a/src/mainboard/emulation/qemu-x86/Options.lb
+++ /dev/null
@@ -1,140 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_COMPRESS
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_WRITE_HIGH_TABLES
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-
-uses CONFIG_UDELAY_IO
-default CONFIG_UDELAY_IO=1
-
-default CONFIG_CONSOLE_SERIAL8250=1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=6
-
-default CONFIG_WRITE_HIGH_TABLES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Option ROM init
-##
-default CONFIG_PCI_ROM_RUN=1
-default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## known-good settings for qemu
-default CONFIG_DCACHE_RAM_BASE=0x8f000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-
-
-
-
-end