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| author | Jonathan Zhang <jonzhang@fb.com> | 2021-02-22 12:17:30 -0800 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-03-10 19:25:05 +0000 |
| commit | 019c0049a27c7eea0b92e8e5af3e5fb992beb315 (patch) | |
| tree | 497beae7924b36f28080cecee96e9cce7077f13b /src/mainboard/facebook/watson/variants/watson_v2/romstage.c | |
| parent | 2f32b5b5d0e0803ca1782d285f16cfae030c89d0 (diff) | |
| download | coreboot-019c0049a27c7eea0b92e8e5af3e5fb992beb315.tar.gz coreboot-019c0049a27c7eea0b92e8e5af3e5fb992beb315.tar.bz2 coreboot-019c0049a27c7eea0b92e8e5af3e5fb992beb315.zip | |
mb/fb/watson: enable IPMI_KCS for watson_v2
For watson_v2 mainboard variant:
* Enable IPMI_KCS in config.
* In early_mainboard_romstage_entry(), enable LPC IO ports
for IPMI over KCS.
Signed-off-by: Ravi Rama <rrama@arista.com>
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ie0e718b44889678c49f3d61cccd0e33b306fc6f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51310
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/facebook/watson/variants/watson_v2/romstage.c')
| -rw-r--r-- | src/mainboard/facebook/watson/variants/watson_v2/romstage.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/facebook/watson/variants/watson_v2/romstage.c b/src/mainboard/facebook/watson/variants/watson_v2/romstage.c index 55f30255e8ec..2e571b971350 100644 --- a/src/mainboard/facebook/watson/variants/watson_v2/romstage.c +++ b/src/mainboard/facebook/watson/variants/watson_v2/romstage.c @@ -15,6 +15,9 @@ * GNU General Public License for more details. */ +#include <device/pci_ops.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> #include <soc/romstage.h> #include <variants.h> @@ -46,3 +49,12 @@ void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData) UpdData->HotPlug_PchPciPort7 = 1; UpdData->HotPlug_PchPciPort8 = 1; } + +void variant_early_mainboard_romstage_entry(void) +{ + // Enable LPC IO ports 0xca2, 0xca8 for IPMI + pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, + (0 << 16) | ALIGN_DOWN(0xca2, 4) | 1); + pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC, + (0 << 16) | ALIGN_DOWN(0xca8, 4) | 1); +} |