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| author | Nico Huber <nico.h@gmx.de> | 2019-07-20 17:03:56 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-20 15:27:01 +0000 |
| commit | ae317695e3f03d55fbba1805ff06e004383e67c8 (patch) | |
| tree | 043aa5f7b46a16df85322a3c38071b0eaa428422 /src/mainboard/getac/p470/devicetree.cb | |
| parent | 0db6e7569da8aff8d868afd65027c075b4710fa4 (diff) | |
| download | coreboot-ae317695e3f03d55fbba1805ff06e004383e67c8.tar.gz coreboot-ae317695e3f03d55fbba1805ff06e004383e67c8.tar.bz2 coreboot-ae317695e3f03d55fbba1805ff06e004383e67c8.zip | |
mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode`4.10
Functional changes were already done in 5eb81bed2e (sb/intel/i82801gx:
Detect if the southbridge supports AHCI) but we forgot to update the
`chip.h` and devicetrees.
Change-Id: I0e25f54ead8f5bbc6041d31347038e800787b624
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34462
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/getac/p470/devicetree.cb')
| -rw-r--r-- | src/mainboard/getac/p470/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index c99455322b45..3135ac435267 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -54,7 +54,7 @@ chip northbridge/intel/i945 register "gpe0_en" = "0x00800106" register "alt_gp_smi_en" = "0x0100" - register "ide_legacy_combined" = "0x1" + register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" |