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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 13:30:29 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-12 08:56:18 +0000 |
| commit | 4c4bd3cd973f3ec20c3a343a183af4a19b97a748 (patch) | |
| tree | 47978f6a48f60e28da38d881733162c665fd68fb /src/mainboard/google/auron | |
| parent | bd72bfece2da38ff60a99a3bbb15bd3243a5d647 (diff) | |
| download | coreboot-4c4bd3cd973f3ec20c3a343a183af4a19b97a748.tar.gz coreboot-4c4bd3cd973f3ec20c3a343a183af4a19b97a748.tar.bz2 coreboot-4c4bd3cd973f3ec20c3a343a183af4a19b97a748.zip | |
soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree
Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/auron')
| -rw-r--r-- | src/mainboard/google/auron/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 3e2f28914563..440efdfd6935 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -15,6 +15,7 @@ chip soc/intel/broadwell register "ec_present" = "true" device cpu_cluster 0 on + ops broadwell_cpu_bus_ops chip cpu/intel/haswell register "s0ix_enable" = "1" @@ -24,6 +25,7 @@ chip soc/intel/broadwell end device domain 0 on + ops broadwell_pci_domain_ops device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio |