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| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-23 16:51:16 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2022-08-14 10:53:47 +0000 |
| commit | 865c97c304af61903f3fad7d489db5097255fe11 (patch) | |
| tree | 6553ab5a609e46ab583253af86abd0ad13e33568 /src/mainboard/google/auron | |
| parent | 4a8cb30222a34de760d38c7d13d54e24221d9fec (diff) | |
| download | coreboot-865c97c304af61903f3fad7d489db5097255fe11.tar.gz coreboot-865c97c304af61903f3fad7d489db5097255fe11.tar.bz2 coreboot-865c97c304af61903f3fad7d489db5097255fe11.zip | |
broadwell: Decouple LPDDR3 DQ/DQS maps from `pei_data`
Introduce the `BROADWELL_LPDDR3` Kconfig option along with some wrapper
code to allow mainboards using LPDDR3 DRAM to supply the DQ/DQS maps to
chipset code without having to use `pei_data`. The only mainboard using
LPDDR3 is Google Samus.
Change-Id: I0aaf0ace243c03600430c2a7ab6389a7b20cb432
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55812
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/auron')
| -rw-r--r-- | src/mainboard/google/auron/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/auron/variants/samus/pei_data.c | 16 | ||||
| -rw-r--r-- | src/mainboard/google/auron/variants/samus/spd/spd.c | 18 |
3 files changed, 19 insertions, 16 deletions
diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 3551be1f8703..c12d9821661c 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_AURON def_bool n select BOARD_ROMSIZE_KB_8192 + select BROADWELL_LPDDR3 if BOARD_GOOGLE_SAMUS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c index b0d9803622bf..705ec25cd880 100644 --- a/src/mainboard/google/auron/variants/samus/pei_data.c +++ b/src/mainboard/google/auron/variants/samus/pei_data.c @@ -1,26 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> -#include <string.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { - /* DQ byte map for Samus board */ - const u8 dq_map[2][6][2] = { - { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, - { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } }, - { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, - { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } }; - /* DQS CPU<>DRAM map for Samus board */ - const u8 dqs_map[2][8] = { - { 2, 0, 1, 3, 6, 4, 7, 5 }, - { 2, 1, 0, 3, 6, 5, 4, 7 } }; - - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - /* P0: HOST PORT */ pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0, USB_PORT_BACK_PANEL); /* P1: HOST PORT */ diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index f12744143b6a..65afe238edc4 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <mainboard/google/auron/variant.h> +#include <soc/pei_wrapper.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> /* Samus board memory configuration GPIOs */ @@ -26,3 +27,20 @@ bool variant_is_dual_channel(const unsigned int spd_index) /* Assume same memory in both channels */ return true; } + +const struct lpddr3_dq_dqs_map *mb_get_lpddr3_dq_dqs_map(void) +{ + static const struct lpddr3_dq_dqs_map lpddr3_map = { + .dq = { + { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, + { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } }, + { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, + { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } }, + }, + .dqs = { + { 2, 0, 1, 3, 6, 4, 7, 5 }, + { 2, 1, 0, 3, 6, 5, 4, 7 }, + }, + }; + return &lpddr3_map; +} |