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| author | Angel Pons <th3fanbus@gmail.com> | 2021-02-11 13:42:20 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-02-12 19:48:26 +0000 |
| commit | 33b59c9170a66a7f6d9c26ccf664714ea81d218d (patch) | |
| tree | f5b71768d08472e1f2f5bea638099601b8e24a37 /src/mainboard/google/beltino | |
| parent | 3b0a4899d8ded1ee9bec1d431d91f431291e3eb0 (diff) | |
| download | coreboot-33b59c9170a66a7f6d9c26ccf664714ea81d218d.tar.gz coreboot-33b59c9170a66a7f6d9c26ccf664714ea81d218d.tar.bz2 coreboot-33b59c9170a66a7f6d9c26ccf664714ea81d218d.zip | |
haswell: Drop `mainboard_fill_pei_data`
Use global variables to provide mainboard USB settings, and have the
northbridge code copy it into the `pei_data` struct. For now.
To minimize diffstat noise, this patch does not reindent the now-global
mainboard USB configuration arrays. This is cleaned up in a follow-up.
Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50538
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/beltino')
| -rw-r--r-- | src/mainboard/google/beltino/romstage.c | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index ee146301eca6..f009f5abe15d 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -46,9 +46,7 @@ void mb_get_spd_map(uint8_t spd_map[4]) spd_map[2] = 0xa4; } -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0064, 1, 0, /* P0: VP8 */ USB_PORT_MINI_PCIE }, @@ -68,14 +66,10 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) USB_PORT_SKIP }, }; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* Enable, OCn# */ { 1, 0 }, /* P1; CN22 */ { 1, 1 }, /* P2; CN23 */ { 1, 2 }, /* P3; CN25 */ { 1, 2 }, /* P4; CN25 */ }; - - memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); -} |