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| author | Aaron Durbin <adurbin@chromium.org> | 2013-08-14 11:31:39 -0500 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 08:56:04 +0100 |
| commit | 7b6cc0403fb00d8795894bb27e9b7faff3fbe130 (patch) | |
| tree | ca693a1b6f4d3be3f39ea72bf5accd5cf25f334d /src/mainboard/google/falco | |
| parent | ebad1765542d63fd873d62fb52ca9e150c9b6291 (diff) | |
| download | coreboot-7b6cc0403fb00d8795894bb27e9b7faff3fbe130.tar.gz coreboot-7b6cc0403fb00d8795894bb27e9b7faff3fbe130.tar.bz2 coreboot-7b6cc0403fb00d8795894bb27e9b7faff3fbe130.zip | |
falco: add rtd2132 settings to device tree
Now that the rtd2132 device has the full settings the
panel timings need to be implemented. Sadly, the Tx timings
in the rtd2132 aren't 1:1 with the panel's Tx timings. Below
is the table equivalent:
RTD2132 | Falco Panel
--------+------------
T1 | T2
--------+------------
T2 | T8+T10+T12
--------+------------
T3 | T14
--------+------------
T4 | T15
--------+------------
T5 | T9+T11+T13
--------+------------
T6 | T3
--------+------------
T7 | T4
--------+------------
Change-Id: I10a3ad475d6b9485a707eb49e31afd197fc8d24d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65858
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4472
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/falco')
| -rw-r--r-- | src/mainboard/google/falco/devicetree.cb | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb index b490d12a4140..4e75c9294838 100644 --- a/src/mainboard/google/falco/devicetree.cb +++ b/src/mainboard/google/falco/devicetree.cb @@ -110,6 +110,27 @@ chip northbridge/intel/haswell device pci 1f.2 on end # SATA Controller device pci 1f.3 on # SMBus chip drivers/i2c/rtd2132 + # Panel Power Timings (1 ms units) + # Note: the panel Tx timings are very + # different from the LVDS bridge + # Tx timing settings. Below is a mapping + # for RTD2132 -> Panel timings. + # T1 = T2 + # T2 = T8 + T10 + T12 + # T3 = T14 + # T4 = T15 + # T5 = T9 + T11 + T13 + # T6 = T3 + # T7 = T4 + register "t1" = "20" + register "t2" = "16" + register "t3" = "1" + register "t4" = "1" + register "t5" = "16" + register "t6" = "20" + register "t7" = "500" + # LVDS Swap settings are normal. + register "lvds_swap" = "0" # Enable Spread Sprectrum at 1.0% register "sscg_percent" = "0x10" device i2c 35 on end |